I have just replaced the original Hynix HY5DU281622ET-J chip with the Micron's 46V32M16-5B F (the smallest SDRAM I could find).

I expected to be having the full 64MB, but instead I have only half of that - 32MB.

My dmesg reports:
...
Determined physical RAM map:
memory: 02000000 @ 00000000 (usable)
on node 0 totalpages 8192
zone (0): 8192
zone (1): 0
zone (2): 0
...
memory: 30420k/32768k available
...

Is it possible to reclaim the remaining half as well?

I did not change any NVRAM variable yet.
Should I force it to recalibrate the DRAM timings?

(My WRT54GL v1.0 is SN#CLA7A0F101902)

Here's what I have in the NVRAM (regarding the RAM):

root@OpenWrt:~# nvram show | grep sdram
size: 2492 bytes (30276 left)
sdram_config=0x0062
sdram_refresh=0x0000
sdram_ncdl=0xfd0009
sdram_init=0x010b
root@OpenWrt:~#

What would you advise to try tweaking?

Is it stable while seeing only 32mb of 64mb?

Yes, right now it is 24 hours of uptime.
I'm sitting behind it on a WiFi WPA2-Enterprize connection.
Seems to be stable...

By the way.
My ISP was assuring me that they have switched me to 1024kbps Up|Dwn link few months ago but I was not perceiving it, I saw ~50~70kBps only.
Since I've put the bigger RAM I can see the 100+kBps now!
Coincidence or not?

(Last edited by booBot on 18 May 2007, 11:25)

I would imagine that is a coincidence ... my WRT54GL runs on a 12Mb connection and never has any problems.

Well it might not be entirely a coincidence.  It depends of the use of the router. My router runs Asterisk, plus a bunch of little utilities like ez-ipupdate & httpd.  When my router is taxed by Bitcomet, my router only has 2% free ram, which I bet is only through serious paging somewhere. When that happens, my upload takes a dive, and my download soon follows.

His router uses already 30 out of 32mb, that means the guy is running heavy stuff

Im highly curious as if it's possible to make the router recognize the other half of that ram chip. Im considering doing the mod as well, and if it's possible to run 64mb, then I'd do the mod with such chip and not 32mb.

Me too!

Ahh, well that makes sense then.

Hmmm...
No!
Actually, the RAM usage shows ~30~40% load.
I do not have any really heavy stuff here (yet). But I plan to!

I'm tempted to try altering the sdram_config from 0x62 to 0xC2, but I do not have the JTAG yet to recover a brick just in case.

(Last edited by booBot on 21 May 2007, 13:54)

http://cgi.ebay.com/JTAG-Cable-to-debri … dZViewItem

or you can make it yourself. I just did mine with 5$'s worth of material and 30 minutes. I wanted to flash the cfe.bin to allow overclocking above 250mhz

Hi booBot

It's been a while since I have done my memory expansion and I don't have enough spare time to work with OpenWRT anymore, which is a pity since I think it's a very cool project. My router is still running happily and provides my internet connection at home (with 32MB of RAM .
Regarding your RAM upgrade, good job! Soldering these quarter pitch SMD's is quite tricky. I also made some inquiries whether it's possible to upgrade to 64MB, but I think I came to the conclusion that there was the fundamental problem, that the additional required address-line was probably not connected-through from the processor. Also, the bootloader never was intended for this much of RAM. It's very simple (software-wise) to upgrade to 32MB because there already is hardware out there that supports that much memory (older hardware-revisions of WRT54GS), so it is detected automatically. However, there are no WRT54Gx-devices that have a default of 64MB RAM, so the bootloader doesn't even attempt to detect it and therefore the additional RAM will not be available to the 'later' parts of the OS.
What you can try to do to enable the full amount of RAM is to recompile the bootloader (it is called 'redmon', I think, and the sources should be available). This may require some understanding of the MIPS microcodes and a cross-compilation environment, probably also a JTAG cable, but it should be possible. There is a similar project on the Linksys NSLU2, where a RAM upgrade from 32MB to 128MB has been achieved (www.nslu2-linux.org --> HowTo --> "FattenYourSlug"). Since this a similar device (with a different processor, though), you may find clues there. Good luck

Hello synthrax!

I hope it is not an address line deficiency, methinks, in the case of a missing line the space penalty would be quadruple - the same line (as far as I can understand) is used twice: once with the RAS, second time with the CAS strobe...

I'll use oscilloscope to check if I have some inactive pins...

I still hope there could be a way to programmatically reconfigure the memory manager layout...

My GS is bricked. So i can remove RAM and Chipset.

If you give me PDF for pinout of chipset et and RAM, I can test the continuity from adresse line to the the chipset, and this for all adress line

We 'll be abble to see how much line are used for addressing ... and so the max RAM chip we can put for an hardware point of view

(Last edited by $@m on 22 May 2007, 14:28)

MT46V32M16
MT46V16M16

You could start with these PDFs.

Thank you in advance!

(as for me - I do not see any difference between the two Micron's pinouts at all... The only difference to HY5DU281622ET is the A12 line - the pin 42...)

(Last edited by booBot on 22 May 2007, 16:26)

yours is MT46V32M16
so 32Mx16 -> 8Mbx16x4bank
-> adressing : A0-A9 for column adresse & A0-A12 for row adresse & BA0-BA1 for bank adresse
5B => PC3200 (3-3-3)
-> adressing : A0-A9 for column adresse (so 10pins)
-> adressing : A0-A12 for row adresse    (so 13pins)
-> adressing : BA0-BA1 for bank adresse

you dont use it

Your are right for A12 (pin42),
but , in your chip, pin 19 and 50 must be float, so if there are wired to ground or Vdd, it s bad for stability but can work.

Original HY5DU281622ET
so 8Mx16 -> 2Mbx16x4bank
-> adressing : A0-A8 for column adresse (so 9pins) => maybe changed by software to adresse A9 **
-> adressing : A0-A11 for row adresse   (so 12pins) => We must have A12 wired to CPU :/
-> adressing : BA0-BA1 for bank adresse => OK

** That explain why you can have 32M.
In fact in the original chip, you can adresse 2^(9x12)=2Mb
with your chip, you can adresse 2^(10x12)=4Mb
A12 is missing to have 2^(10x13)=8Mb

To conclude : tomorrow, if possible, I 'll remove Chip Ram to see a wire under Pin42. If there is not.... you are going to be F...d :(
If there is, maybe a soft modification will be possible to adresse 8Mb :D

(Last edited by $@m on 23 May 2007, 11:21)

Yes, I do not use the 46V16M16, I just got it's pinout to see if there are differences to the larger capacity chip...

I read (elsewhere) that the A12 trace to the CPU is there.

Waiting impatiently for your confirmation...

(Last edited by booBot on 23 May 2007, 12:44)

oki,
I notice that the size after there is a A13 (1GB).

I took my WRT this midday (it was midday in france ) so I will do it these next 5h

(Last edited by $@m on 23 May 2007, 13:18)

Oki :
Bad news :

1) on GS the RAM chip is 55Pin not 66 => Pinout is not full compliant
2) on GS the A12 is NOT wired, juste a foot print.

So to have 64M, you must have a RAM with more column pin adress A0-A10
and for 128, A0-A11, but I don't know if that exists...

To finish, i learn something : Data port is not common for the 2 chips. all 16 data pins from 2 chip are wired to 32 chipset pins, so
we must have 2 chip because datas are on 32bits

For me a 64MB Hack on GS (1.0) is not possible, Maybe on G ??

But perhaps a Flash Hack 4 to 8 Mb... but without chipset pinout, impossible to answer... and with SD mod... no utility...

(Last edited by $@m on 23 May 2007, 16:41)

I'm preparing to try the TE28F640J3C instead of the current TE28F320J3C.

I received my new GS (v1.1), there is only 1 RAM chip HY5DU561622DT 16MBx16 !!

Have you one or 2 RAM chips ?

And your Flash chip is a 48 or 56 pins ?

(Last edited by $@m on 24 May 2007, 10:55)

Yes, there is only one set of 66 pads, so I have only one RAM chip.

I did not count but the Intel's PDF says: the TE chips have 56 pins. (GE chips have 48 pins)
There are three of four sets of pads for the FLASH chip - several different casings will fit in. (It is difficult to tell how many sitting paces are there without unsoldering the current chip first. I'll do it as soon as I find the bigger FLASH)

(Last edited by booBot on 24 May 2007, 14:59)

So...finally...we'll have only 32mb?

Yes for the moment

the original 16MB of WRT54GL there are adressing : A0-A8 for column adresse, 9bit
but your 64MB MT46V32M16 there are adressing : A0-A9 for column adresse, 10bit

Refer from http://wl500g.dyndns.org/sdram.html in sdram_init table original are set
to 9bit in ColWidth (sdram_init=0x010b ) you have to set to 10bit (0x0113)

root@(none)# nvram show | grep sdram
sdram_config=0x0062
sdram_refresh=0x0000
sdram_ncdl=0xff0008
sdram_init=0x010b

and then you repace new 0x0113 to sdram_init then commit to NVRAM.

nvram set sdram_init=0x0113 (this sets the variable)
nvram commit (this writes the change to flash memory, making it permanent)

I,m noop, but i hope you will try and feedback to me .  ^^!

sorry for my bad english ..

(Last edited by Oishikawa on 28 May 2007, 15:49)