You can find the right modules on a KVR400X64SC3A/512
Topic: WRT54GL and 64MB RAM upgrade: [partial] success.
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hutarios wrote:
You can find the right modules on a KVR400X64SC3A/512
For sure ?
xtrem57 wrote:
hutarios wrote:You can find the right modules on a KVR400X64SC3A/512
For sure ?
This document seems to concur
I would not bet on it, but the KVR400X64SC3A does not look like a pure coincidence.
However - one should consult the relevant PDF for every chip found on any double-sided eight-chip module, just in case.
Here are some photos of my toolchain.
hutarios wrote:
You can find the right modules on a KVR400X64SC3A/512
chip => 8x HYB25D512800CE-5
pdf => http://www.qimonda.com/download.jsp?ref … 31_www.pdf
i was wondering why it's possible to replace sdram chips with ddr-ram!?
I just read http://www.nslu2-linux.org/wiki/HowTo/FattenYourSlug
So is it possible to mod the nslu2 also with tsop-chips from ddr so-dimm modules?
it is already DDR in fact 
what do you mean?
On the first page/post is written SDRAM! So in many other posts...
Reading your link makes me think that NSLU2 indeed uses the SDRAM.
SDRAMs are not interchangable with DDRs.
on wrt, it is : DDR SDRam (the right complete name, cut to DDR, in common language)
maybe NSLU2 : it is just SDRam... (old ram)
(Last edited by $@m on 16 Jul 2007, 09:46)
Seeking advice here.
I bought 3 of these chips from digikey:
http://www.digikey.com/scripts/DkSearch … -1212-1-ND
Tried upgrading 2 different routers. Even removed and tried again the same router.
Routers are WRT54GL.
In all cases, a no go. Routers don't boot and console is blank.
I then put back the original RAM chip on one of the routers and presto, boots fine and works as before the mod attempt.
Any ideas?
(Last edited by nekmech on 28 Jul 2007, 10:30)
Hmmm...
These ICs look perfectly right - the same as I use here.
"Should work".
Are you sure you did not make any mistakes soldering them? (pinning errors, short-circuits, etc)
booBot wrote:
Hmmm...
These ICs look perfectly right - the same as I use here."Should work".
Are you sure you did not make any mistakes soldering them? (pinning errors, short-circuits, etc)
Pretty sure which is why I did it 3 times.
I'm also sure I didn't rip any pads. Even took photos of the PCB's without the RAM and zoomed on the PC to check.
Can't understand what I'm doing wrong, especially since cleaning up the original chip and soldering it in, works.
About ready to tear my hair out..
You didn't do anything special apart from just removing the original and soldering in the new chip, did you?
I saw on the PDF that pins 19,50 are supposed to be NC.
I think I'll order some more from Jameco and try again.
I tried to find SODIMMS for a while but gave up on that.
Thanks booBot really just trying to confirm these were the right chips.
All I did was to unsolder a chip off a SoDIMM, remove the excessive solder and flux off it's pins.
Then I used the same hot-air gun to unsolder the original chip off the PCB, cleaned the pads.
As soon as I soldered the new chip and cleaned the PCB - no extra wires or capacitors|resistors added - the device was usable (with only the 32MB, as described earlyer in this thread).
My WRT65GL is v1.0, a friend of mine brought his WRT54GL v1.1 - the same success - we both now have the 64MB RAM on our boxen.
It must because of some error, either the chips you've bought are defective. If you could obtain the fourth chip - you probably could put them on a SoDIMM to test in a PC...
nekmech wrote:
Seeking advice here.
I bought 3 of these chips from digikey:
http://www.digikey.com/scripts/DkSearch … -1212-1-NDTried upgrading 2 different routers. Even removed and tried again the same router.
Routers are WRT54GL.
In all cases, a no go. Routers don't boot and console is blank.I then put back the original RAM chip on one of the routers and presto, boots fine and works as before the mod attempt.
Any ideas?
This happened to me while I was attempting a RAM upgrade on a La Fonera. The chip was new (so it hadn't been previously soldered), yet despite examining EVERY pad under a microscope, the device wouldn't boot. The original still worked fine. I also used the other two chips, from the same lot, on two more Fonera's that are working just fine.
It could have just been a bad part, or you may have inadvertently damaged it with with ESD.
I tried all 3 chips I bought on 2 different routers.
No way I can know if I damaged them all with ESD, but if the original chips work after soldering them back in, then either I'm lucky the original chips didn't get damaged too, or the new parts are more susceptible to ESD damage.
Haven't given up on this upgrade yet....
Has anyone had any luck with an elpida DD5116ADTA. This appears to be a 32Mb x 16 TSOP chip which I have 8 mounted on a 512MB DDR 333 laptop SO-DIMM. I can't seem to locate a data sheet anywhere online for this particular revision to compare it to the Micron chip mentioned in this thread. I did find a data sheet on a DD5116AFTA here: http://www.elpida.com/pdfs/E0699E50.pdf. Looks like the only difference is the revision of the chip. Anyone have any insight before I take the plunge and try de-soldering these chips.
Got mad...
I would like to upgrade my WRT54GL v1.1, but couldn't understand what kind of RAM should I use.
I've TONS of DIMMs and DDR, which should I use? and which SPEED??? 100Mhz,133Mhz? 233Mhz?
Any help is welcome!
I went and got one of those Kingston Modules (KVR400X64SC3A/512) and mine has Nanya NT5DS32M16BS Chips.
I removed the Chips from the SODIMM using a hot air gun. For the GL, I had some trouble with the method from video2_tsop48.wmv and damaged some pads without actually removing the chip. 
Using thin copper wire, I bent up all pins of the old Hynix chip. I then soldered in the new Nanya chip and connected the missing pads to vias using the thin coated copper wire. The router booted up fine (with 32MB), however after changing the nvram values it doesn't boot anymore (nothing on the serial console). Looks like I'll have to make a hairydairymaid cable. Maybe I should have just changed sdram_init without touching sdram_ncdl. I'd expect if the current timing works, the number of cas lines used shouldn't make a difference. 
At least I'm pretty sure I can get it to boot again (wrote down the old nvram values), then I'll have to look if the 32MB configuration is really ok/stable and try changing sdram_ncdl again.
Does someone know the meaning of the ncdl bits? Might be nice to be able to tweak them manually instead of relying on the automated tweaking by the CFE...
I'm afraid, the wires that go underneath the PCB a way too long...
You'd better try to reach these vias on the same side of the PCB as the chip sits (from the underneath of the chip itself rather than the PCB).
(Last edited by booBot on 6 Nov 2007, 18:01)
booBot wrote:
I'm afraid, the wires that go underneath the PCB a way too long...
You'd better try to reach these vias on the same side of the PCB as the chip sits (from the underneath of the chip itself rather than the PCB).
Well, it's booting again though.
Using the hairydairymaid JTAG tool I was able to erase the nvram (using the custom flash command, despite detecting a 4MB flash it wanted to read/write nvram from somewhere around 2MB).
The reason it wasn't booting anymore was a nonsense value in sdram_init (0x0519 instead of 0x0113), which didn't have the '16bit interface' flag set (as documented on http://wl500g.dyndns.org/sdram.html).
Now I put the right value into nvram and it is detecting all 64MB of ram (despite the overly long copper to /ras and /cas and /we). I also changed sdram_config to 0x0032 (CL 3 instead of CL 2.5, as the Kingston module is supposed to be CL3 and because of the long copper wire ), now I've got to do some stability tests...
[edit]
Since the cache line size is 16 Bytes (according to linux boot messages) I upped sdram_config to 0x0033 (8 word burst instead of 4 word burst, should mean 16 bytes per burst I think).
I wonder how fast the memory is clocked?
The old hynix chip was a -J, which according to the datasheet I have means DDR333; 133MHz@CL2 or 166MHz@CL2.5 (2.5-3-3) or 166MHz@CL3 (3-3-3)
And the old sdram_config value was for CL2.5.
The new Nanya chip is a -5T (DDR400); 166MHz@CL2.5 or 200MHz@CL3
I'd assume the memory clock is either 100MHz or 200MHz and the latter looks rather unlikely, given the hynix specs.
Also, the (non-ddr) sdram memory in my WRT54GS is rated for at most 143MHz@CL3 or 100MHz@CL2. Here sdram_config is 0x0022 (burst 4, CL2).
So, the new Nanya memory is really way too fast, maybe I should lower CL back to 2.5 or even 2 and look at the longterm stability.
OTOH that may be the reason it even works at all given the long connections to the bottom vias...
[/edit]
[edit2]
Hmm, no openwrt memtester package. But Debian memtester-2.93.1 compiles fine with make CC=mipsel-linux-uclibc-gcc.
Looking good so far:
root@OpenWrt:~# /tmp/memtest 50M
memtest v. 2.93.1
(C) 2000 Charles Cazabon <memtest@discworld.dyndns.org>
Original v.1 (C) 1999 Simon Kirby <sim@stormix.com> <sim@neato.org>
Current limits:
RLIMIT_RSS 0x7fffffff
RLIMIT_VMEM 0x8000
Raising limits...
Allocated 52428800 bytes...trying mlock...success. Starting tests...
Testing 52424704 bytes at 0x2abe1000 (4088 bytes lost to page alignment).
Run 1:
Test 1: Stuck Address: Testing...Passed.
Test 2: Random value: Setting...Testing...Passed.
Test 3: XOR comparison: Setting...Testing...Passed.
Test 4: SUB comparison: Setting...Testing...Passed.
Test 5: MUL comparison: Setting...Testing...Passed.
Test 6: DIV comparison: Setting...Testing...Passed.
Test 7: OR comparison: Setting...Testing...Passed.
Test 8: AND comparison: Setting...Testing...Passed.
Test 9: Sequential Increment: Setting...Testing...Passed.
Test 10: Solid Bits: Testing...Passed.
Test 11: Block Sequential: Setting... 147[/edit2]
(Last edited by moroboshi on 10 Nov 2007, 19:57)
Ok, since I was curious about the DRAM performance, I wrote a small linear read speed testing tool:
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#define MB 8ULL /* allocate 8MB */
#define LOOPS 32
#define SIZE (1024*1024*MB)
static int quiet = 0;
void die(char *msg)
{
fprintf(stderr, "%s\n", msg);
exit(1);
}
void say(char *msg)
{
if (!quiet) fprintf(stderr, "%s\n", msg);
}
int main(int argc, char **argv)
{
struct timeval tv1, tv2, tv3, tv4;
long long t1, t2, t3, t4;
int i, j, k;
int *mem;
quiet = argc > 1;
if (!quiet) fprintf(stderr, "Allocating %d MB... ", MB);
mem = malloc(SIZE);
if (mem == NULL) {
die("malloc failed");
} else {
say("ok");
}
if (!quiet) fprintf(stderr, "Renicing to -20... ");
if (nice(-20) == -1) {
say("nice(-20) failed");
} else {
say("ok");
}
for (k=2; k>0; k--) { /* loop twice, to make sure we are hot */
gettimeofday(&tv1, NULL);
for (j=LOOPS; j>0; j--) {
/**
* Unrolled loop for memory read bandwidth testing.
* Using 8 registers is overkill, but doesn't hurt either.
* 2 would probably suffice here.
**/
asm(".set noreorder\n"
".set nomacro\n"
"move $2, %0\n"
"li $3, %1\n"
// ".align 4\n" /* 2^4 == 16 */
"loop:\n"
"addiu $3,$3,-32 \n"
"lw $8, 0x00($2) \n"
"lw $9, 0x04($2) \n"
"lw $10, 0x08($2) \n"
"lw $11, 0x0c($2) \n"
"lw $12, 0x10($2) \n"
"lw $13, 0x14($2) \n"
"lw $14, 0x18($2) \n"
"lw $15, 0x1c($2) \n"
"lw $8, 0x20($2) \n"
"lw $9, 0x24($2) \n"
"lw $10, 0x28($2) \n"
"lw $11, 0x2c($2) \n"
"lw $12, 0x30($2) \n"
"lw $13, 0x34($2) \n"
"lw $14, 0x38($2) \n"
"lw $15, 0x3c($2) \n"
"lw $8, 0x40($2) \n"
"lw $9, 0x44($2) \n"
"lw $10, 0x48($2) \n"
"lw $11, 0x4c($2) \n"
"lw $12, 0x50($2) \n"
"lw $13, 0x54($2) \n"
"lw $14, 0x58($2) \n"
"lw $15, 0x5c($2) \n"
"lw $8, 0x60($2) \n"
"lw $9, 0x64($2) \n"
"lw $10, 0x68($2) \n"
"lw $11, 0x6c($2) \n"
"lw $12, 0x70($2) \n"
"lw $13, 0x74($2) \n"
"lw $14, 0x78($2) \n"
"lw $15, 0x7c($2) \n"
"bgtz $3,loop \n" /* note: delayed branching */
"addiu $2,$2,128 \n" /* address is incremented in delay slot of branch */
".set macro \n"
".set reorder \n"
:
: "r" (mem),
"i" (SIZE/sizeof(*mem))
: "$2", "$3",
"$8", "$9", "$10", "$11",
"$12", "$13", "$14", "$15");
}
gettimeofday(&tv2, NULL);
}
t1 = tv1.tv_sec;
t1 *= 1000000ULL;
t1 += tv1.tv_usec;
t2 = tv2.tv_sec;
t2 *= 1000000ULL;
t2 += tv2.tv_usec;
for (k=2; k>0; k--) { /* loop twice, to make sure we are hot */
gettimeofday(&tv1, NULL);
for (j=LOOPS; j>0; j--) {
/**
* Unrolled loop for L1 read bandwidth testing
* Using 8 registers is overkill, but doesn't hurt either.
* 2 would probably suffice here.
* This is a copy of the previous loop, with the
* address increment replaced by 0.
**/
asm(".set noreorder\n"
".set nomacro\n"
"move $2, %0\n"
"li $3, %1\n"
// ".align 4\n" /* 2^4 == 16 */
"loop2:\n"
"addiu $3,$3,-32 \n"
"lw $8, 0x00($2) \n"
"lw $9, 0x04($2) \n"
"lw $10, 0x08($2) \n"
"lw $11, 0x0c($2) \n"
"lw $12, 0x10($2) \n"
"lw $13, 0x14($2) \n"
"lw $14, 0x18($2) \n"
"lw $15, 0x1c($2) \n"
"lw $8, 0x20($2) \n"
"lw $9, 0x24($2) \n"
"lw $10, 0x28($2) \n"
"lw $11, 0x2c($2) \n"
"lw $12, 0x30($2) \n"
"lw $13, 0x34($2) \n"
"lw $14, 0x38($2) \n"
"lw $15, 0x3c($2) \n"
"lw $8, 0x40($2) \n"
"lw $9, 0x44($2) \n"
"lw $10, 0x48($2) \n"
"lw $11, 0x4c($2) \n"
"lw $12, 0x50($2) \n"
"lw $13, 0x54($2) \n"
"lw $14, 0x58($2) \n"
"lw $15, 0x5c($2) \n"
"lw $8, 0x60($2) \n"
"lw $9, 0x64($2) \n"
"lw $10, 0x68($2) \n"
"lw $11, 0x6c($2) \n"
"lw $12, 0x70($2) \n"
"lw $13, 0x74($2) \n"
"lw $14, 0x78($2) \n"
"lw $15, 0x7c($2) \n"
"bgtz $3,loop2 \n" /* note: delayed branching */
"addiu $2,$2,0 \n" /* address is incremented in delay slot of branch */
".set macro \n"
".set reorder \n"
:
: "r" (mem),
"i" (SIZE/sizeof(*mem))
: "$2", "$3",
"$8", "$9", "$10", "$11",
"$12", "$13", "$14", "$15");
}
gettimeofday(&tv2, NULL);
}
t3 = tv1.tv_sec;
t3 *= 1000000ULL;
t3 += tv1.tv_usec;
t4 = tv2.tv_sec;
t4 *= 1000000ULL;
t4 += tv2.tv_usec;
#define ADJUST1 35 /* inner loop has 32 loads in 35 instructions */
#define ADJUST2 32 /* inner loop has 32 loads in 35 instructions */
printf("%d loops over %dMB in %lld usecs: %lld.%02lld MB/s\n",
(int)LOOPS, (int)MB,
t2 - t1,
(LOOPS*MB*1000000ULL*ADJUST1)/(t2-t1)/ADJUST2,
((100ULL*LOOPS*MB*1000000ULL*ADJUST1)/(t2-t1)/ADJUST2)%100ULL);
printf("L1: %lld.%02lld MB/s\n",
(LOOPS*MB*1000000ULL*ADJUST1)/(t4-t3)/ADJUST2,
((100ULL*LOOPS*MB*1000000ULL*ADJUST1)/(t4-t3)/ADJUST2)%100ULL);
free(mem);
}This is the result on the WRT54GL (16bit DDR RAM):
root@wrt54gl64:/# /tmp/wrtramspeed
Allocating 8 MB... ok
Renicing to -20... ok
32 loops over 8MB in 383013 usecs: 731.04 MB/s
L1: 759.62 MB/sAnd this is on my WRT54GS (32bit SDRAM)
root@wrt54gs:~# /tmp/wrtramspeed
Allocating 8 MB... ok
Renicing to -20... ok
32 loops over 8MB in 439148 usecs: 637.59 MB/s
L1: 744.71 MB/sTheoretical maximum for L1 speed should be 800MB/s (200MHz times 4bytes per load instruction / 1 clock cycle per instruction).
This would seem to point to a ~180 MHz memory clock for the GL and a ~160 MHz memory clock for the GS (well, if the code is working as I expect, that is).
_If_ this is approximately correct, then memory is overclocked in both cases (Hynix DDR rated for 166MHz, ISSI SDRAM rated for 143 MHz).
Hi, I'd like to report that I just successfully upgraded a WRT54G v2.2 to 64MB of RAM. It had the same Hynix chip as my WRT54GL, which I replaced with one of the NanYa chips.
It first detected 32MB as expected and after changing to
sdram_config=0x0063
sdram_ncdl=0
sdram_init=0x0113it now runs happily with all 64MB usable (However I haven't done any longterm stability tests so far).
Sorry, posts 101 to 100 are missing from our archive.
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