For check.
I have established it between these points.
In a photo it is not present!

go irc #AR7

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AndyI has added a section "WatchDog Disable Point" to http://wiki.openwrt.org/OpenWrtDocs/Hardware/ADLS2110HR where my question has been answered.

So, if you ADD the resistor, it disables the watchdog?

yes

Hi,

Sinus 154 DSL Basic SE (TNETD7300) has an initial value of 0x025d4291. The watchdog works.
"Initial" is the value read from the boot loader's command prompt (most boot loaders support memory dumps).

The value changes when an operating system is running. It also depends on the router's endianess (see below).

Here is an extract from ar7.c (part of the AR7 emulation for QEMU) which shows the bit values:

typedef enum {
    CONFIG_BOOTS = BITS(2, 0),          /* 001 */
    CONFIG_WSDP = BIT(3),               /* 0 */
    CONFIG_WDHE = BIT(4),               /* 0 */
    CONFIG_PLL_BYP = BIT(5),            /* 0 */
    CONFIG_ENDIAN = BIT(6),             /* 0 = little endian */
    CONFIG_FLASHW = BITS(8, 7),         /* 01 = 16 bit flash */
    CONFIG_EMIFRATE = BIT(9),           /* 1 */
    CONFIG_EMIFTEST = BIT(10),          /* 0 */
    CONFIG_BOOTS_INT = BITS(13, 11),    /* 000 */
    CONFIG_SYS_PLL_SEL = BITS(15, 14),  /* 01, BUS */
    CONFIG_CPU_PLL_SEL = BITS(17, 16),  /* 01 */
    CONFIG_USB_PLL_SEL = BITS(19, 18),  /* 11 */
    CONFIG_EPHY_PLL_SEL = BITS(21, 20), /* 01 */
    CONFIG_DSP_PLL_SEL = BITS(23, 22),  /* 01, ADSL */
    CONFIG_ADSL_RST = BIT(24),          /* 0 */
    CONFIG_MIPS_ASYNC = BIT(25),        /* 1 */
    CONFIG_DEF = BIT(26),               /* 0 */
    CONFIG_RESERVED = BITS(31, 27),     /* 0 */
} dcl_config_bit_t;

With AR7 emulation, you can also trace read/write access to this register.

Thanks

I have no idea how you found where to put the resistor.

Interesting.

DG834v2 [NOT G]
CPU revision is: 00018448 (MIPS 4KEc)
bootcr is 0x2594281
Clocks: prediv: 1, postdiv: 1, mul: 10
TI AR7 (TNETD7300), ID: 0x0005, Revision: 0x02

So the watchdog is disabled on your router?  (bit 4 is 0).

yeah

CPU revision is: 00018448 (MIPS 4KEc)
bootcr 7300 is 0x2514281
TI AR7 (TNETD7300), ID: 0x0005, Revision: 0x27
0x2514281 100101000101000010100-0-0001 disable
After change R59 place.
0x2514291 100101000101000010100-1-0001 enable!

see picture
6. WatchDog Enable
http://wiki.openwrt.org/OpenWrtDocs/Har … LS2110HR_7