Basic POST completed...     Success.

Last reset cause: Software reset (memory controller also reset)



PSPBoot1.4 rev: 1.4.0.4

(c) Copyright 2002-2005 Texas Instruments, Inc. All Rights Reserved.



Press ESC for monitor... 3321



(psbl) 



Booting...

Linux version 2.6.24.2 (horinek@eddy) (gcc version 4.1.2) #1 Fri Apr 4 21:07:47 CEST 2008

console [early0] enabled

CPU revision is: 00018448 (MIPS 4KEc)

Clocks: Sync 2:1 mode

Clocks: Setting CPU clock

Adjusted requested frequency 211000000 to 211968000

Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6

Clocks: Setting DSP clock

Clocks: base = 25000000, frequency = 105984000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10

Clocks: Setting USB clock

Adjusted requested frequency 48000000 to 47863741

Clocks: base = 105984000, frequency = 48000000, prediv = 1, postdiv = 31, postdiv2 = -1, mul = 14

TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x10

Determined physical RAM map:

 memory: 01000000 @ 14000000 (usable)

Initrd not found or empty - disabling initrd

Zone PFN ranges:

  Normal      81920 ->    86016

Movable zone start PFN for each node

early_node_map[1] active PFN ranges

    0:    81920 ->    86016

Built 1 zonelists in Zone order, mobility grouping off.  Total pages: 4064

Kernel command line: init=/etc/preinit rootfstype=squashfs,jffs2, console=ttyS0,9600n8

Primary instruction cache 16kB, VIPT, 4-way, linesize 16 bytes.

Primary data cache 8kB, 4-way, VIPT, no aliases, linesize 16 bytes

Synthesized clear page handler (26 instructions).

Synthesized copy page handler (46 instructions).

Synthesized TLB refill handler (20 instructions).

Synthesized TLB load handler fastpath (32 instructions).

Synthesized TLB store handler fastpath (32 instructions).

Synthesized TLB modify handler fastpath (31 instructions).

PID hash table entries: 64 (order: 6, 256 bytes)

Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)

Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)

Memory: 12504k/16384k available (2036k kernel code, 3880k reserved, 432k data, 128k init, 0k highmem)

Mount-cache hash table entries: 512

net_namespace: 64 bytes

NET: Registered protocol family 16

Time: MIPS clocksource has been installed.

NET: Registered protocol family 2

IP route cache hash table entries: 1024 (order: 0, 4096 bytes)

TCP established hash table entries: 512 (order: 0, 4096 bytes)

TCP bind hash table entries: 512 (order: -1, 2048 bytes)

TCP: Hash tables configured (established 512 bind 512)

TCP reno registered

squashfs: version 3.0 (2006/03/15) Phillip Lougher

Registering mini_fo version $Id$

JFFS2 version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.

io scheduler noop registered

io scheduler deadline registered (default)

Serial: 8250/16550 driver $Revision: 1.90 $ 2 ports, IRQ sharing disabled

serial8250: ttyS0 at MMIO 0x8610e00 (irq = 15) is a TI-AR7

---- here is lot of empty lines ----


Basic POST completed...     Success.

Last reset cause: Software reset (memory controller also reset)



PSPBoot1.4 rev: 1.4.0.4

(c) Copyright 2002-2005 Texas Instruments, Inc. All Rights Reserved.