Hi,

Someone can help me please?

Thanks,
Xavier

Try this way: https://forum.openwrt.org/viewtopic.php … 18#p228918
Copy to /tmp folder instead to RAM.

Hello,

Thanks pepe2k for sharing your excellent work.

Quick question for everyone, is there any additional tweaking (to the source) that can be made to further speed up boot time? Thanks

KK

Anyone knows the formula for PLL Calculation?
I don't get the NINT and NFRAC parts...

Remove U-Boot, move low level initialization to kernel.

Hi Pepe2k I just examine the comments in ap121.h about the PLL Calculations.
In db12x.h
#define CFG_PLL_FREQ                CFG_PLL_560_480_240
then I look in ar934x_soc.h

First since the clock crystal is 40MHZ PLL = ((40 MHz / REFDIV) * DIV_INT) / (2 ^ OUTDIV)
Base on the values
40/1 * 14 / 2^1 =  560/2 but the CPU is 560?
Also I have change the config value from 14 to 15 but after I flash and boot clk frequency is still 560Mhz?

Also base on the calculation we are suppose to have 560_480_240 but when booting it is 560_450_225?

AFAIR, clocks/PLL calculation for AR934x are different.

I haven't yet got time to fix clocks configuration and make it working (so that you could just choose configuration) for this target. Take a look at this code:
https://github.com/pepe2k/u-boot_mod/bl … 34x.S#L142

Yes, I will update my code with new formulas.

My Router WDR4300 is stable at 730_480_240.
At 740 memtest occasionally fails.

My opinion is that to tune performance we just need to look at wr1043ndv2
The specs of that router is 720_600_200
AHB_POST_DIV is set to 2 so AHB divides by 3.
I am not sure the effects of DDR frequency on performance this is something interesting to look into.

You should make some stress tests with USB. It's the first thing which became unstable with higher AHB clock.
I have here WDR3600 which is working on 800/500/250 for couple of months

There are a lots more possibilities for PLL/clocks configurations than on AR9331.
You can use CPU or DDR PLL as a source for all three main clocks (CPU, AHB, DDR), you have there more dividers... etc., etc.

The problem is simple - no time for that at this moment And one more thing - there is some mysterious "SRIF" block with other PLLs and I couldn't find any information about it... (take a look here: https://patchwork.linux-mips.org/patch/4324/).

But my unit is different from yours...
At 780_480_240 it doesn't boot but yours does so maybe my unit has a lousy chip...
Btw the WR1043NDV2 comes with mip74kc v5.0 and their DDR2 is clocked at 600MHz AHB 200 (DDR/3) higher then mod AHB to DDR / 2

(Last edited by alphasparc on 26 May 2014, 17:22)

Winbond memory chips?

Yes, new QCA SoCs can work on higher clocks, but they are similar to previous Atheros SoCs (AR9344 -> QCA9558).

Yes...Winbond 8MB
What I mean is that we should set our AHB Divisor to 2 so we can set our memory higher while still keeping AHB low.

(Last edited by alphasparc on 26 May 2014, 17:39)

Memory, not FLASH!

It's not a problem with AHB.

Sorry mine is Hynix RAM.

I get always best results with Samsung chips and worst... with Winbond.

Is tplink TL-WDR3600 supported? I have newly bought hardware v1.5 of the router (green leds) and have already soldered the pins to have the serial console working. The github page says the router is supported but wanted to confirm before I go ahead with it as I am new to all this and do not have any means to recover if I brick it. If supported, please let me know where can I download the precompiled binaries and whether the steps on the github page works for this router as well. Thanks.

Yes.

You need to download the sources and compile them or use old version, available in "release" section on GitHub.

Sorry for stupid question, but why should i use dd-wrt if openwrt have mtd command too? Thanks.

Because "uboot" mtd partition in official OpenWRT builds is read only.

If you want to use OpenWRT to upgrade the uboot you can compile a custom OpenWRT firmware with uboot unlocked.
IMO OpenWRT did it right by setting it to read-only this will prevent accidental (or malicious) erase of uboot partition on production systems.

Just remove this line in tplinkpart.c

   art_offset = master->size - TPLINK_ART_LEN;

   parts[0].name = "u-boot";
   parts[0].offset = 0;
   parts[0].size = offset;
--parts[0].mask_flags = MTD_WRITEABLE;

  parts[1].name = "kernel";
  parts[1].offset = offset;
  parts[1].size = rootfs_offset - offset;

Both uboot and art partitions are protected in OpenWrt in the same manner

(Last edited by alphasparc on 9 Jun 2014, 14:00)

Thanks, flashed it and it works very well. The precompiled one meets my requirements for now. Will compile and flash new once overclocking is stabilized.

Thanks again for your efforts.

I have 2 MR3420v2
One has HW Version 2.1 the other has HW Version 2.4
You'd expect them to be the same but they are not
HW Version 2.1 comes with AR9341 Rev1 and HW Version 2.4 comes with AR9341 Rev3
And the occasional boot fails occur on the HW Version 2.4 even though I copied the uboot from the one with HW Version 2.1 and changed the MAC and the WPS.
Why is this so weird?

I have no idea, maybe new revision of the SoC is different and needs some changes in code.

I observed that they have different hardware watchpoint...after booting
Which chip revision do you have? (/dev/cpuinfo or dmesg)
I have
Atheros AR9344 rev 2
Atheros AR9341 rev 1
Atheros AR9341 rev 3

(Last edited by alphasparc on 10 Jun 2014, 11:32)

At this moment I don't have any AR9341 based device here.
Anyway, there is no AR9341 datasheet public available, so it will require a lot of effort to track down and solve this problem. And what's more, TP-Link doesn't update their GPL code center, so even if they make some changes for new SoC revision, we won't know about that.