OpenWrt Forum Archive

Topic: Nexx WT3020: upgrading flash storage, with pictures

The content of this topic has been archived between 6 Apr 2018 and 5 May 2018. There are no obvious gaps in this topic, but there may still be some posts missing at the end.

I decided that I wanted to upgrade this router's onboard flash from 8M to 16M (and possibly beyond if possible) because:
1. I like the small form factor
2. it's a great value at ~$17 from aliexpress
3. I hit the built-in storage limit pretty quickly and still wasn't able to add all the modules I wanted. Yes I know about extroot, but the point about this small router is that... it's small, and portable, and pocketable. With extroot it wouldn't be anymore.

So I studied the boot log (https://dl.dropboxusercontent.com/u/107 … utty.log.2) and this version uses an Eon EN25Q64 64Mbit chip (datasheet: http://www.eonssi.com/upfile/p2009111114954.pdf) instead of the W25Q64BV referenced on http://wiki.openwrt.org/toh/nexx/wt3020. No problem, they are compatible. The next chip up from Winbond is a 128Mbit SPI W25Q128FV http://www.nexflash.com/NR/rdonlyres/A5 … Q128FV.pdf which I was able to find at Digi-Key (http://www.digikey.com/product-detail/e … ND/3008697) for $25 for 10 pieces including shipping.

I got the package in the mail today and got to hacking.

1: the original board showing the SPI EEPROM with markings scratched off from factory (heh). The green wires are for the serial console.
https://dl.dropboxusercontent.com/u/107843342/wt3020/1.jpg

2: required for hacking smile
https://dl.dropboxusercontent.com/u/107843342/wt3020/2.jpg

3: chip unsoldered.
https://dl.dropboxusercontent.com/u/107843342/wt3020/3.jpg

4. original chip in carrier ready to be read. I used a TL866A USB EEPROM reader to make a copy of the original firmware for safekeeping (if you need it you can download it here: https://dl.dropboxusercontent.com/u/107 … are237.7z)
https://dl.dropboxusercontent.com/u/107843342/wt3020/4.jpg

5. replacement chips
https://dl.dropboxusercontent.com/u/107843342/wt3020/5.jpg

6. New larger 16MB chip soldered in; old chip below. Before soldering it I flashed it with the original firmware.
https://dl.dropboxusercontent.com/u/107843342/wt3020/6.jpg

And serial console log showing that the bootloader complains about not knowing what the new chip is, but keeps booting anyway. https://dl.dropboxusercontent.com/u/107 … utty.log.3

Now onto making openwrt use all that extra flash. smile

(Last edited by stamasd on 24 Dec 2014, 02:31)

Grr, been trying to build an openwrt image for 16M from the current sources, but it appears that the git tree is broken right now.  It gives me broken dependencies not finding libbfd-2.24.so, libopcodes-2.24.so and libz.so.1 (which BTW I do have on my build system)

Package objdump is missing dependencies for the following libraries:
libbfd-2.24.so
libopcodes-2.24.so
libz.so.1

(Last edited by stamasd on 24 Dec 2014, 15:55)

Success! I managed to compile an image from git r43771 and flashed it over the original firmware. All of the 16MB flash are usable, with ~12MB available on / with no packages installed except Luci.

Filesystem           1K-blocks      Used Available Use% Mounted on
rootfs                   12608       472     12136   4% /
/dev/root                 2304      2304         0 100% /rom
tmpfs                    30752       516     30236   2% /tmp
tmpfs                    30752        56     30696   0% /tmp/root
tmpfs                      512         0       512   0% /dev
/dev/mtdblock5           12608       472     12136   4% /overlay
overlayfs:/overlay       12608       472     12136   4% /

If anyone wants to try this mod, here are the compiled images (with Luci built-in):
https://dl.dropboxusercontent.com/u/107 … actory.bin
https://dl.dropboxusercontent.com/u/107 … pgrade.bin

And the .dts that I used to compile this:

/dts-v1/;

/include/ "mt7620n.dtsi"

/ {
    compatible = "wt3020", "ralink,mt7620n-soc";
    model = "Nexx WT3020";

    palmbus@10000000 {
                gpio2: gpio@660 {
                        status = "okay";
                };

                gpio3: gpio@688 {
                        status = "okay";
                };

        spi@b00 {
            status = "okay";

            m25p160@0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "w25q128";
                reg = <0 0>;
                linux,modalias = "m25p160", "w25q128";
                spi-max-frequency = <10000000>;

                partition@0 {
                    label = "u-boot";
                    reg = <0x0 0x30000>;
                    read-only;
                };

                partition@30000 {
                    label = "u-boot-env";
                    reg = <0x30000 0x10000>;
                    read-only;
                };

                factory: partition@40000 {
                    label = "factory";
                    reg = <0x40000 0x10000>;
                    read-only;
                };

                partition@50000 {
                    label = "firmware";
                    reg = <0x50000 0xfb0000>;
                };
            };
        };
    };

    ehci@101c0000 {
        status = "okay";
    };

    ohci@101c1000 {
        status = "okay";
    };

    ethernet@10100000 {
        mtd-mac-address = <&factory 0x4>;
        ralink,port-map = "wllll";
    };

    wmac@10180000 {
        ralink,mtd-eeprom = <&factory 0>;
    };

    pinctrl {
        state_default: pinctrl0 {
            default {
                ralink,group = "ephy", "wled", "pa", "i2c", "wdt", "uartf";
                ralink,function = "gpio";
            };
        };
    };

    gpio-keys-polled {
        compatible = "gpio-keys-polled";
        #address-cells = <1>;
        #size-cells = <0>;
        poll-interval = <20>;
        reset {
            label = "reset";
            gpios = <&gpio0 1 1>;
            linux,code = <0x198>;
        };
    };

        gpio-leds {
                compatible = "gpio-leds";
                power {
                        label = "nexx:blue:power";
                        gpios = <&gpio3 0 0>;
                };
        };
};

I would like to attempt next to upgrade the flash even further, to 32MB or even 64MB. The problem with that is that nobody seems to manufacture 32MB or 64MB flash chips in SOIC-8 package - they are all in SOIC-16 or DFN/BGA, even though only 8 pins are used. It's not impossible but it's not a simple desolder/resolder project as it will require building an adapter

(Last edited by stamasd on 25 Dec 2014, 22:21)

Is there any calibration data and/or MAC address on the chip that needs to be preserved when flashing the new chip? On Atheros-based systems, there is an "ART partition" for that.

probono wrote:

Is there any calibration data and/or MAC address on the chip that needs to be preserved when flashing the new chip? On Atheros-based systems, there is an "ART partition" for that.


Well if you look through the boot log it has the following snippet:

Creating 4 MTD partitions on "raspi":
0x000000000000-0x000000030000 : "Bootloader"
0x000000030000-0x000000040000 : "Config"
0x000000040000-0x000000050000 : "Factory"
0x000000050000-0x000000800000 : "Kernel"

I assume that the factory partition contains calibration data. That partition is preserved when flashing, and it is also defined in the .dts that I posted. Of course, the factory partition being at the beginning of the chip makes it easy to expand to larger chips.

I have ordered and am currently awaiting delivery of some 256Mbit and 512Mbit SPI flash chips; like I said, there aren't any in 8-SOIC package, but I found some in WSON (8x6mm) package which should be solderable with a bit of luck onto a 8-SOIC pad pattern. Flashing them in my programmer is another matter though, I don't have an appropriate carrier and that may be a problem.

Also while I'm waiting for the chips I have built images with 64MB flash chip support, download below. Also with built-in Luci.
https://dl.dropboxusercontent.com/u/107 … actory.bin
https://dl.dropboxusercontent.com/u/107 … pgrade.bin

(Last edited by stamasd on 2 Jan 2015, 19:57)

stamasd wrote:

4. original chip in carrier ready to be read. I used a TL866A USB EEPROM reader to make a copy of the original firmware for safekeeping (if you need it you can download it here: https://dl.dropboxusercontent.com/u/107 … are237.7z)
https://dl.dropboxusercontent.com/u/107843342/wt3020/4.jpg

6. New larger 16MB chip soldered in; old chip below. Before soldering it I flashed it with the original firmware.
https://dl.dropboxusercontent.com/u/107843342/wt3020/6.jpg

Hello stamasd,
can I ask what SPI programmer and what software program you used to program your chips? I am new at this but would like to follow your mod.
I can get a CH341A based SPI programmer (this one) but don't know if it will work. Also, what software to use to flash the chip? Ponyprog? Other?

Thank you very much!

jamdat wrote:

Hello stamasd,
can I ask what SPI programmer and what software program you used to program your chips? I am new at this but would like to follow your mod.
I can get a CH341A based SPI programmer (this one) but don't know if it will work. Also, what software to use to flash the chip? Ponyprog? Other?

Thank you very much!

It's in my top post somewhere. I use a TL866A and its own software (from http://www.autoelectric.cn/minipro/ ) I got it off ebay for about $50.

The programmer you linked to may or not work, but it doesn't come with the right adapter. The SOIC-8 adapter they include with that one requires that the chip be soldered to it for programming. I use a ZIF-type adapter, see my picture above (or like this one: http://www.aliexpress.com/item/New-Univ … 72257.html ). You do not want to solder/unsolder those chips too many times.

There are also clamp-style adapters like this: http://www.aliexpress.com/item/IC-clamp … 23061.html which supposedly can be used to program a chip without desoldering, but I haven't used one and don't know how well would work.

probono wrote:

Possibly if you have an Arduino you could use that to flash a SPI flash?
http://flashrom.org/Serprog/Arduino_flasher
(I have not tested it yet)

Sure, it should work. It doesn't take much to program a SPI device.

(Last edited by stamasd on 2 Jan 2015, 22:52)

Well I received some N25Q512 devices in the mail... bad news, I wasn't able to use them.

1. they wouldn't fit in my SOIC-8 programming adapter. The WSON package is compatible with the SOIC-8 pad pattern, but the device is physically larger and doesn't fit. Strike one.

2. I soldered it to a SOIC-8 pad adapter and plugged it into my programmer. It's not supported. The programmer can read the device ID (and complain that it doesn't know what it is), read, and write the first 128 bytes... once. It can't erase the device. Strike two.

3. I attempted to use an Arduino-based programmer for SPI, despite it reportedly only supporting chips up to 16MB/128Mb only. All I wanted to do is flash the 64MB chip with the 8MB of the original firmware, so it should work, right? Well I get this

./flashrom  -V -p serprog:dev=/dev/ttyUSB0:115200
flashrom v0.9.7-r1860 on Linux 3.8.0-44-generic (x86_64)
flashrom is free software, get the source code at http://www.flashrom.org

flashrom was built with libpci 3.1.8, GCC 4.6.3, little endian
Command line (3 args): ./flashrom -V -p serprog:dev=/dev/ttyUSB0:115200
Calibrating delay loop... OS timer resolution is 1 usecs, 2973M loops per second, 10 myus = 10 us, 100 myus = 108 us, 1000 myus = 1002 us, 10000 myus = 10145 us, 4 myus = 6 us, OK.
Initializing serprog programmer
Baud rate is 115200 now.
serprog: connected - attempting to synchronize
........Error: cannot synchronize protocol - check communications and reset device?
Error: Programmer initialization failed.

I was half-expecting that, since in the meantime I had read the N25Q512 datasheet, and it appears that it uses a special protocol for programming.
Last strike. I'm out.

Well for now at least. I have 2 more things planned:

A. Getting a programmer that supports 512Mbit chips. One such is in the mail, a Blackcat USB which per the description specifically supports the N25Q512 chip. http://www.ebay.com/itm/Blackcat-USB-SP … 43a37548b0 We shall see.

B. a few W25Q256 chips (256Mbit/32Mbyte) flash chips are on a slowboat from China. If all else fails I hope those will work. I'll know in a month or so.

However... I have very little hope to actually make the N25Q512 chips useful. The bootloader would have to support their special adressing mode, and chances are slim that it does.
The bootloader is reportedly U-boot v.1.1.3 from January 2013. Does anyone know if it supports 512Mbit flash chips, specifically the stacked devices from Micron?
If not, it looks like I may have to replace the original u-boot with something else, either a newer U-boot or another bootloader. This is turning into a fairly big project. sad


(edit) according to the Ralink SDK manual which I found at http://wendang.baidu.com/view/553c114af … af004.html the MT7620 chip itself does support 512Mbit flash devices, which is good news. There is hope yet. smile

(Last edited by stamasd on 3 Jan 2015, 22:02)

The 256 has a compatibility mode where the first 16 MB can be accessed with the old commands (24 bit address, which can only access a 16 MB space), as if it were a 16 MB chip.  I don't know about the 512.

mk24 wrote:

The 256 has a compatibility mode where the first 16 MB can be accessed with the old commands (24 bit address, which can only access a 16 MB space), as if it were a 16 MB chip.  I don't know about the 512.

That is interesting, The 512Mb chip should support that also, given that in fact it's comprised of 2x256Mbit chips stacked. smile

This is my first boot log after flashing uboot image compiled from MTK_Ralink_ApSoC_SDK_4110.

Router booting without any problem but this uboot code need some  modification to work well with wt3020. I don't know anything about coding, anyone interested ? 
   

U-Boot 1.1.3 (Jan  8 2015 - 18:44:26)

Board: Ralink APSoC DRAM:  64 MB
relocate_code Pointer at: 83fb4000
enable ephy clock...done. rf reg 29 = 5
SSC disabled.
spi_wait_nsec: 29
spi device id: ef 40 18 0 0 (40180000)
Warning: un-recognized chip ID, please update bootloader!
raspi_read: from:30000 len:1000
raspi_read: from:30000 len:1000
============================================
Ralink UBoot Version: 4.1.1.0
--------------------------------------------
ASIC 7620_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: 16 MBytes NOR Flash
Date:Jan  8 2015  Time:18:44:26
============================================
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 580 MHZ ####
 estimate memory size =64 Mbytes
raspi_read: from:50000 len:40
raspi_read: from:850000 len:40

=================================================
Check image validation:
Image1 Header Magic Number --> OK
Image2 Header Magic Number --> Failed
Image1 Header Checksum --> OK
Image1 Data Checksum --> raspi_read: from:50040 len:11c4b9
OK
Image1 Stable Flag --> Not stable
Image1 Try Counter --> 9

Image1 is not stable and try counter > 3. Take it as a broken image.
Image1: Broken Image2: Broken
Upgrade Mode~~

=================================================

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     0

3: System Boot system code via Flash.
## Booting image at bc050000 ...
raspi_read: from:30000 len:10000
Erasing SPI Flash...
raspi_erase: offs:30000 len:10000
.
Writing to SPI Flash...
raspi_write: to:30000 len:10000
.
done
raspi_read: from:50000 len:40
   Image Name:   MIPS OpenWrt Linux-3.14.26
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    1164473 Bytes =  1.1 MB
   Load Address: 80000000
   Entry Point:  80000000
raspi_read: from:50040 len:11c4b9
   Verifying Checksum ... OK
   Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 80000000) ...
## Giving linux memsize in MB, 64

Starting kernel ...

[    0.000000] Linux version 3.14.26 (silviu@Monster) (gcc version 4.8.3 (OpenWr                                                     t/Linaro GCC 4.8-2014.04 r43771) ) #1 Thu Dec 25 12:11:49 EST 2014
[    0.000000] Board has DDR1
[    0.000000] Analog PMU set to hw control
[    0.000000] Digital PMU set to hw control
[    0.000000] SoC Type: Ralink MT7620N ver:2 eco:6
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 00019650 (MIPS 24KEc)
[    0.000000] MIPS: machine is Nexx WT3020
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 04000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x00000000-0x03ffffff]
[    0.000000] Movable zone start for each node
.
.
.
.
saturn-b wrote:

This is my first boot log after flashing uboot image compiled from MTK_Ralink_ApSoC_SDK_4110.

Router booting without any problem but this uboot code need some  modification to work well with wt3020. I don't know anything about coding, anyone interested ?


Do you have the SDK? I've been looking for it but was unable to find it so far. Actually I think a newer revision exists too, 4.2.0.0

(Last edited by stamasd on 9 Jan 2015, 01:44)

stamasd wrote:

Do you have the SDK? I've been looking for it but was unable to find it so far. Actually I think a newer revision exists too, 4.2.0.0

I found it on chinese site , there is plenty of MT7620 data files if you interested, plese visit Here or just google it "MTK_Ralink_ApSoC_SDK_4110_20121102.tar"

(Last edited by saturn-b on 9 Jan 2015, 05:09)

Hm, if "2012110" is the date of release then this SDK is older than the firmware in the WT3020... any leads on a newer SDK?

stamasd wrote:

Hm, if "2012110" is the date of release then this SDK is older than the firmware in the WT3020... any leads on a newer SDK?

You can find at panbaidu for MTK_Ralink_ApSoC_SDK_4200_20131106.tar.bz2

Trying to download but ftp server prevent me to download after some times.

After adding spi flash id to uboot sc , flash ic became recognize by uboot.

U-Boot 1.1.3 (Jan 10 2015 - 18:10:31)

Board: Ralink APSoC DRAM:  64 MB
relocate_code Pointer at: 83fb4000
enable ephy clock...done. rf reg 29 = 5
SSC disabled.
spi_wait_nsec: 29
spi device id: ef 40 18 0 0 (40180000)
find flash: W25Q128FV
raspi_read: from:30000 len:1000
raspi_read: from:30000 len:1000
============================================
Ralink UBoot Version: 4.1.1.0
--------------------------------------------
ASIC 7620_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: SPI Flash
Date:Jan 10 2015  Time:18:10:31
============================================
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768

 ##### The CPU freq = 580 MHZ ####
 estimate memory size =64 Mbytes

Please choose the operation:
   1: Load system code to SDRAM via TFTP.
   2: Load system code then write to Flash via TFTP.
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial.
   9: Load Boot Loader code then write to Flash via TFTP.                     0

3: System Boot system code via Flash.
## Booting image at bc050000 ...
raspi_read: from:50000 len:40
   Image Name:   MIPS OpenWrt Linux-3.14.26
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    1164473 Bytes =  1.1 MB
   Load Address: 80000000
   Entry Point:  80000000

My problem when using your firmware always produce "jffs2: Newly-erased block contained word...." , are you facing the same problem ?

Nope, I haven't seen that message at all.

Failsafe
if the 192.168.1.1 interface does not respond, the only chances to debrick are serial or tftp firmware uploads. Both need soldering the serial cables ...

without failsafe the only chance to debrick is with serial cables attached and http://wiki.openwrt.org/doc/howto/gener … ing.serial

or tftp method http://wiki.openwrt.org/doc/howto/generic.flashing.tftp
like with WR703n http://forums.openpilot.org/blog/52/ent … fi-router/

(Last edited by cave on 22 Jan 2015, 14:53)

just use any of bootloaders with tftp/web recovery.

Failsafe mode works by applying dirty hacks :

Index: target/linux/ramips/base-files/lib/preinit/07_set_preinit_iface_ramips
===================================================================
--- target/linux/ramips/base-files/lib/preinit/07_set_preinit_iface_ramips    (revision 44078)
+++ target/linux/ramips/base-files/lib/preinit/07_set_preinit_iface_ramips    (working copy)
@@ -6,12 +6,12 @@
 . /lib/ramips.sh
 
 ramips_set_preinit_iface() {
-    RT3X5X=`cat /proc/cpuinfo | egrep "(RT3.5|RT5350|MT7628)"`
+    RT3X5X=`cat /proc/cpuinfo | egrep "(RT3.5|RT5350|MT7628|MT7620)"`
     if [ -n "${RT3X5X}" ]; then
         swconfig dev rt305x set reset 1
     fi
 
-    if echo $RT3X5X | egrep -q "(RT5350|MT7628)"; then
+    if echo $RT3X5X | egrep -q "(RT5350|MT7628|MT7620)"; then
         # This is a dirty hack to get by while the switch
         # problem is investigated. When VLAN is disabled, ICMP
         # pings work as expected, but TCP connections time

- failsafe -


BusyBox v1.22.1 (2015-01-22 22:35:02 WIB) built-in shell (ash)
Enter 'help' for a list of built-in commands.

ash: can't access tty; job control turned off
  _______                     ________        __
 |       |.-----.-----.-----.|  |  |  |.----.|  |_
 |   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
 |_______||   __|_____|__|__||________||__|  |____|
          |__| W I R E L E S S   F R E E D O M
 -----------------------------------------------------
 CHAOS CALMER (Bleeding Edge, r44078)
 -----------------------------------------------------
  * 1 1/2 oz Gin            Shake with a glassful
  * 1/4 oz Triple Sec       of broken ice and pour
  * 3/4 oz Lime Juice       unstrained into a goblet.
  * 1 1/2 oz Orange Juice
  * 1 tsp. Grenadine Syrup
 -----------------------------------------------------
================= FAILSAFE MODE active ================
special commands:
* firstboot         reset settings to factory defaults
* mount_root     mount root-partition with config files

after mount_root:
* passwd             change root's password
* /etc/config            directory with config files

for more help see:
http://wiki.openwrt.org/doc/howto/generic.failsafe
=======================================================

root@(none):/# [   42.290000] random: nonblocking pool is initialized

root@(none):/# ping -c 3 192.168.1.20
PING 192.168.1.20 (192.168.1.20): 56 data bytes
64 bytes from 192.168.1.20: seq=0 ttl=64 time=0.280 ms
64 bytes from 192.168.1.20: seq=1 ttl=64 time=0.220 ms
64 bytes from 192.168.1.20: seq=2 ttl=64 time=0.200 ms

--- 192.168.1.20 ping statistics ---
3 packets transmitted, 3 packets received, 0% packet loss
round-trip min/avg/max = 0.200/0.233/0.280 ms
root@(none):/# 

thank, saturn-b. so, what's about your uboot? i'm really interested in it and want to try.

hackru wrote:

thank, saturn-b. so, what's about your uboot? i'm really interested in it and want to try.

It's not mine , I just made minor mod. from CleanWRT uboot github based on pepe2k uboot work.

saturn-b wrote:
hackru wrote:

thank, saturn-b. so, what's about your uboot? i'm really interested in it and want to try.

It's not mine , I just made minor mod. from CleanWRT uboot github based on pepe2k uboot work.

Anyway, can you provide binary to test?

hackru wrote:
saturn-b wrote:
hackru wrote:

thank, saturn-b. so, what's about your uboot? i'm really interested in it and want to try.

It's not mine , I just made minor mod. from CleanWRT uboot github based on pepe2k uboot work.

Anyway, can you provide binary to test?

Sure https://app.box.com/s/56r84jn7slzmz7i0j531zuaig1pk2gdx

U-Boot 1.1.3 (Jan 19 2015 - 00:59:23)

Board: Ralink APSoC DRAM:  64 MB
GPIO#44 updated GPIOMODE register: 001a311c -> 001ab11c
NEXX WT-3020 gpio init : WPS / RESET pin
GPIO#1 updated GPIOMODE register: 001ab11c -> 001ab11d
relocate_code Pointer at: 83fac000
enable ephy clock...done. rf reg 29 = 5
SSC disabled.
spi_wait_nsec: 29 
spi device id: ef 40 18 0 0 (40180000)
find flash: W25Q128FV
raspi_read: from:30000 len:1000 
raspi_read: from:30000 len:1000 
============================================ 
CleanWRT u-boot_mt7620 Version: 0.0.0.3
-------------------------------------------- 
ASIC 7620_MP (Port5<->None)
DRAM component: 512 Mbits DDR, width 16
DRAM bus: 16 bit
Total memory: 64 MBytes
Flash component: SPI Flash
Date:Jan 19 2015  Time:00:59:23
============================================ 
icache: sets:512, ways:4, linesz:32 ,total:65536
dcache: sets:256, ways:4, linesz:32 ,total:32768 

 ##### The CPU freq = 580 MHZ #### 
 estimate memory size =64 Mbytes

Press press RESET button for more than 2 seconds to run web failsafe mode

RESET button is pressed for:  0 second(s)reset button pressed!
 1 second(s)reset button pressed!
reset button pressed!
 2 second(s)

RESET button was pressed for 2 seconds
HTTP server is starting for firmware update...

raspi_read: from:40028 len:6 


 NetTxPacket = 0x83FE3580 

 NetRxPackets[0] = 0x83FE3B80

 NetRxPackets[1] = 0x83FE4180

 NetRxPackets[2] = 0x83FE4780

 NetRxPackets[3] = 0x83FE4D80

 NetRxPackets[4] = 0x83FE5380

 NetRxPackets[5] = 0x83FE5980

 NetRxPackets[6] = 0x83FE5F80

 NetRxPackets[7] = 0x83FE6580

 NetRxPackets[8] = 0x83FE6B80

 NetRxPackets[9] = 0x83FE7180

 NetRxPackets[10] = 0x83FE7780

 NetRxPackets[11] = 0x83FE7D80

 NetRxPackets[12] = 0x83FE8380

 NetRxPackets[13] = 0x83FE8980

 NetRxPackets[14] = 0x83FE8F80

 NetRxPackets[15] = 0x83FE9580

 NetRxPackets[16] = 0x83FE9B80

 NetRxPackets[17] = 0x83FEA180

 NetRxPackets[18] = 0x83FEA780

 NetRxPackets[19] = 0x83FEAD80

 NetRxPackets[20] = 0x83FEB380

 NetRxPackets[21] = 0x83FEB980

 NetRxPackets[22] = 0x83FEBF80

 NetRxPackets[23] = 0x83FEC580

 KSEG1ADDR(NetTxPacket) = 0xA3FE3580 

 NetLoopHttpd,call eth_halt ! 
Trying Eth0 (10/100-M)

 Waitting for RX_DMA_BUSY status Start... done


 ETH_STATE_ACTIVE!! 
HTTP server is starting at IP: 192.168.0.111
HTTP server is ready!

(Last edited by saturn-b on 22 Jan 2015, 23:33)