Arrgggg, I am so very confused and am really hoping that someone can jump in here and help me understand something that I have spent two days trying to figure out:
 
  I know, from reading the AR9331 datasheet and both the book See MIPS Run and MIPS32 24Kc Processor Core Datasheet, that upon reset the
MIPS based CPU puts out an address of 0xBFC00000 which is mapped to the flash address space or internal ROM code; however, what I cant find any
documentation on is the "fact?" that the SPI flash memory starts at 0x9F000000 (which is where the bootstrap and uboot code is based at) and
the DDR memory is at 0x80000000.  So if I am going to breadboard a new MIPS system, how am I supposed to verify that the addresses 0x9F000000 and
0x80000000 is really where the SPI flash and DDR memory maps to?

Now I know that I can always find configuration information in either the u-boot code or linker scripts from such things as Open-wrt but I also know
that there has to be some documentation that either defines the address for the SPI/DDR or allows you to calculate the proper address (if I am designing a
new BSP, I cant just guess and hope for the best).

I am sure that the answer to clearing the fog out of my brain is probably right in front of my face but it appears that I have spent too much time digging through
too many books and datasheets to understand this, so I would greatly appreciate it if someone could help me out here I would greatly appreciate it as I am going crazy not
being able to pin down exactly where the addresses 0x9F000000 and 0x80000000 come from.

I just want to say, What a difference a day of rest makes!  Having given up on my pursuit of trying to figure out the 0x9F000000 address question for a day (had to do farming chores) the fog on the brain has cleared.  For those of you who may find yourself in the same state of mind let me take a few seconds to answer my own question from above:

The reason that the start of SPI flash memory is at 0x9F000000 and the starto f DDR Memory is at 0x80000000 has to do with the fact that each of these addresses falls within the kseq0 address space of the MIPS processes and because of such the translation from the virtual addresses of 0x9F000000 and 0x80000000 to physical addresses is done "by subtracting 0x80000000 from the virtual address" (MIPS32 24K Processor Core Family Software User's Manual, Revision 03.11 pg 96) which gives us a physical address of 0x1F000000 and 0x00000000.

Now if we take these two physical addresses (0x1F000000 and 0x00000000) and apply the defined AR9331 Address Map (AR9331 802.11n 1x1 2.4 GHz SoC for AP and Router Platforms, pg 23) we see that the Serial Flash is mapped to the physical address range 0x1F000000-0x1FFFFFFF while the DDR Space is mapped to the physical address 0x00000000-0x0FFFFFFF.

See, just like I mentioned in my first post, the answer to my question was something simple.  I guess that will teach me to spend all day focusing on multiple concepts (by the time I hit this one my head was full of mush). 

I hope this answer helps someone else down the road.