@pepe2k,
Could you provide some tips for compiling RAM (non-relocatable) version of your u-boot?
This would be very helpful, because RAM version could be loaded via standard u-boot, without burning the flash. It gives a very safe way of testing and debugging. Thanks.

I'm sorry, but I don't know U-Boot very well, so I don't know how to do this... please, see also this FAQ answer:
http://www.denx.de/wiki/view/DULG/CanUBootBeConfiguredSuchThatItCanBeStartedInRAM

You probably did not use search.
https://forum.openwrt.org/viewtopic.php?pid=193078#p193078
https://forum.openwrt.org/viewtopic.php?id=33205

What is so difficult to understand that U-Boot for AP121 platform is different from U-Boot for other platforms with architecture AR71xx...? It's not the same code! At 0x01FD00 offset in flash there is a model number for these routers (MR3020/3040/WR703N...) NOT a value for PLL register setting.

If you know how to make U-Boot to get setting for PLL register from flash and how to prepare version which can start from RAM... just download the code, do it and let us know about your results.

(Last edited by pepe2k on 26 Apr 2013, 14:37)

hi all:
how can i find out the serial point (TX,RX,GND) on PCB board with ar9331?
my router is tplink 741n v4 ,the image links:
https://lh6.googleusercontent.com/-JiPL … 192117.jpg

omg, have you read wiki for 741???

I just upgrade my 3220v2 boot loader with this u-boot and works well , I'm doing upgrade process from u-boot console, here's the log :

=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2013.04.27 21:59:42 =~=~=~=~=~=~=~=~=~=~=~=

U-Boot 1.1.4 (Nov 20 2012 - 15:40:01)

AP121 (ar9330) U-boot

DRAM:  32 MB
led turning on for 1s...
id read 0x100000ff
flash size 16777216, sector count = 256
Flash: 16 MB
Using default environment

In:    serial
Out:   serial
Err:   serial
Net:   ag7240_enet_initialize...
blah blah blah ...
blah blah blah ...
blah blah blah ...
No valid address in Flash. Using fixed address
No valid address in Flash. Using fixed address
: cfg1 0x5 cfg2 0x7114
eth0: 00:03:7f:09:0b:ad
ag7240_phy_setup 
eth0 up
: cfg1 0xf cfg2 0x7214
eth1: 00:03:7f:09:0b:ad
athrs26_reg_init_lan
ATHRS26: resetting s26
ATHRS26: s26 reset done
ag7240_phy_setup 
eth1 up
eth0, eth1
Autobooting in 3 seconds

hornet> erase 0x9f000000 +0x10000


First 0x0 last 0x0 sector size 0x10000
   0
Erased 1 sectors
hornet> tftpboot 0x81000000 uboot.bin

eth1 link down
Using eth0 device
TFTP from server 192.168.1.2; our IP address is 192.168.1.1
Filename 'uboot.bin'.
Load address: 0x81000000
Loading: *#############
done
Bytes transferred = 65536 (10000 hex)
hornet> cp.b 0x81000000 0x9f000000 0x10000

Copy to Flash... write addr: 9f000000
done



hornet> reset 

*****************************************
*      U-Boot 1.1.4  (Apr 22 2013)      *
*****************************************

AP121 (AR9331) U-Boot for TL-MR3020

DRAM:  32 MB
FLASH: Winbond W25Q128 (16 MB)

LED on during eth initialization...

Hit any key to stop autobooting:  1 0 

Booting image at: 0x9F020000...
Uncompressing kernel image...
OK
Starting kernel...

Nice
What about reset button? Does it work? I didn't check what GPIOs are used in MR3220v2 for LEDs and reset button... but I will do it and make version dedicated for this model.

Yes it works too :

*****************************************
*      U-Boot 1.1.4  (Apr 22 2013)      *
*****************************************

AP121 (AR9331) U-Boot for TL-MR3020

DRAM:  32 MB
FLASH: Winbond W25Q128 (16 MB)

LED on during eth initialization...

Press reset button for at least:
- 3 sec. to run web failsafe mode
- 5 sec. to run U-Boot console
- 7 sec. to run U-Boot netconsole

Reset button is pressed for:  0  1  2  3  4  5  6  7  8  9 

Button was pressed for 9 sec...
Starting U-Boot netconsole...

*****************************************
*      U-Boot 1.1.4  (Apr 22 2013)      *
*****************************************

AP121 (AR9331) U-Boot for TL-MR3020

DRAM:  32 MB
FLASH: Winbond W25Q128 (16 MB)

LED on during eth initialization...

~»¿¿ÿ¿  66666666þþþPress reset button for at least:
- 3 sec. to run web failsafe mode
- 5 sec. to run U-Boot console
- 7 sec. to run U-Boot netconsole

Reset button is pressed for:  0  1  2  3 

Button was pressed for 3 sec...
HTTP server is starting for firmware update...

Ethernet mode (duplex/speed): 1/100 Mbps
HTTP server is starting at IP: 192.168.1.1
HTTP server is ready!

(Last edited by xopal on 27 Apr 2013, 17:01)

I previously wrote one person on this subject (this), but the processor was different - but a positive result is the same.
To be honest, I'm happy to dig into yours source code, but do not have time.

I will upload the major/base changes that I made for the AP96 platform.
Based on the changes(changes between the original and RAM mod Uboot) and this sources, I hope you understand the issue.

In patch or sources:
Where all "SKIP_LOWLEVEL_INIT" = U-boot RAM mod

In source:
Where CFG_PLL_OFFSET, CFG_PLL_MAGIC = responsible for the variable of CPU frequency.

P.S.
I'm sorry for my terrible English.

(Last edited by Dioptimizer on 4 May 2013, 23:47)

Exactly how I write the bootloader to an 8MB Flash chip (SST25VF064, 8 pin SOIC version) using Flashrom and a Bus Pirate? (As in what settings to get the bootloader to the correct part of Flash.) I'm upgrading a TL-WR702N (already did the RAM) and I already took out the old Flash chip and read it out to a file. Besides the bootloader itself, what else do I need to copy over so it can boot?

You don't really need a programmer, just use uboot and connect your flash chips like that: https://forum.openwrt.org/viewtopic.php?pid=179169#p179169
Essentially you need the uboot partition right at the start of the flash and the ART partition all the way at the end (original position + 4 MB).

OK, I understand what you want to get but I'm afraid that option "SKIP_LOWLEVEL_INIT" isn't exist in U-Boot 1.1.4 (which is used by TP-Link) for AR7240... so it needs to be added. Maybe I will try.

I don't think (but maybe I'm wrong!) also that setting new frequency for PLL and dividers for CPU/DDR/AHB on AR9331 is so simple like in the code you pointed to (just writing prepared register value into PLL setting register):

ar7240_reg_wr(AR7240_CPU_PLL_CONFIG,cfgpll);

It needs to be tested because Assembler section for PLL initialization in original sources is bigger and contains more PLL and dividers registers operations.

For now I'm thinking about new command in U-Boot console for PLL clock and CPU/DDR/AHB dividers manipulation, just for testing if we can change these values simply by changing proper registers, without reset the CPU and changing also other registers.

All you need to do is just erase whole chip (fill it with 0xFF) and put my U-Boot image at offset 0x0 (beginning of the FLASH). The ART image you can upload later in web panel. You need also to copy 64 KiB (from offset 0x10000) data from your original flash - this block contains MAC address and model number. Please, refer to the following flash layout:

But, for now in my U-Boot modification you FLASH won't be recognized properly and you won't be able to upload ART image! I will add it in next couple of days. Please, provide me full chip mark.

Here's the datasheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/25036B.pdf

I did a hexdump of the original image and the MAC address is at 0x001e0000. What is the original Flash layout of the WR-702N so I can copy the config?

I'm an electrical engineer so I already have the programmer (Bus Pirate).

OK, could you also check with Bus Pirate the JEDEC ID for your chip (I need to know if it is the same as in datasheet).

The offset is different than in other TP-Link products. I checked the wiki and I found that this model uses VxWorks and different bootloader so you cannot simply move config/content from old flash if you want to use my U-Boot version and OpenWrt.

I think that you should try to run this router with flash content copied from any WR703N, just change MAC address which should be at 0x0001FC00. If you want, I can give you whole original flash dump from my 703N, with my U-Boot.

Probably, you should also add support for this model in OpenWrt sources but... in my opinion this model isn't interesting - it needs FLASH and RAM MOD to run OpenWrt and even after that you get device without USB. The 703N isn't more expensive and has 4M/32M and USB already included

It does match.

Could you upload a copy of a WR703N config page? (You can change the MAC to something like 12:34:56:78:90 if you don't want to post that.) I don't have a WR703N. I got the WR702N because it was on sale ($15) at a local store. Even if I got the WR703N, I would be upgrading it anyways.

(Last edited by NiHaoMike on 6 May 2013, 14:10)

The first thing to do is to assume that the ar9331 has at its core processor ar7241:
Setting the frequency with reboot (for u-boot is critical and provided as an example):
http://www.google.com/translate_c?langp … g%2525jtag

Installing without restarting the CPU frequency selective (later from the company Compex, file init-ar7240.mac)
http://www.cpx.cz/dls/wpe72_WPE72NX_MMJ5N26E/wp72_loader_jtag.zip
Source

Analogue for uboot commands:
md 0x1 <address>
mw <address> <value>

For example default PLL setup:

mw 0xb8050000 0x00040828
mw 0xb8050008 0x1
mw 0xb8050008 0x0

(Last edited by Dioptimizer on 6 May 2013, 15:55)

Are you definitely sure that different Atheros SoCs with the same core CPU has same CPU/DDR/AHB PLL configuration registers?

I know how to use these commands in U-Boot... but I still don't get it what do you want to achieve? In my opinion, overclocking AR9331 with 25 MHz oscillator doesn't make any sens, because of very limited different dividers configurations!

If you want, you can write PM to me in Russian and explain what you want to achieve.

You can verify this by reading the memory address:

md 0x1 0xb8050000

If the frequency of your CPU 400/400/200
value mus be same - 0x00040828

And I'm not talking about the fact that you will give something from overclocking.
The discussion began with what seemed to you to deal with the complex registers responsible for the overclocking. (If I understand correctly)
https://forum.openwrt.org/viewtopic.php?pid=200787#p200787

Nope, you are wrong. This commands just hang the router... Please, refer to AR9331 datasheet. 0x00040828 value is not proper for CPU_PLL_CONFIG register! For example (information from datasheet):

"Bits 9:0 - Reserved. Must be written with zero. Contains zeros when read."

In your value (0x00040828) bits 0...9 aren't 0...

NO! You are wrong... Just read the AR9331 datasheet... PLEASE, read the documentation!

In MR3020:

uboot> md.b 0xb8050000 4

B8050000: 00 81 80 00    ....

Do you understand now that different SoCs, even with the same CPU core, could have different registers, missing registers and different settings for PLL configuration?

(Last edited by pepe2k on 6 May 2013, 16:44)

I hard coded the Flash to 8MB and it works great. BTW, for those trying to find a config page, don't bother. Just tack on 64kB of 0xFFs and then put in the model number and MAC address.

@pepe2k,dimonix:

I will try to give a RAM version when I have time.

Hi,pepe2k
Can you make the same uboot for AR9341(such as TL-WR841N V8,TL-WR843)

I don't have any device with this SoC, so I don't have chance to test it.

I'm working now at version for AR9344 (WDR3600/4300/4310) with O/C option in U-Boot console and recovery mode on reset button.

Very good news you've got here pepe2k. I'm interested to try it.