Topic: U-Boot mod for routers with AR9331/AR9344

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Post #51

johnyin.news

17 May 2013, 14:04

wr703n v1.6 works!!

Post #52

pepe2k

17 May 2013, 14:06

johnyin.news wrote:

wr703n v1.6 works!!

Yes, I know... I have already tested it on: TL-WR703N ver. 1.5, 1.6 and 1.7

Post #53

Davidwei

18 May 2013, 01:14

Hi,pepe2k
i download your sources code frome http://www.tech-blog.pl/pliki/u-boot_sources_for_tp-link_AR9331_by_pepe2k.tar.gz
but i dont know how to build.the follwing is my adm
1.make the new uboot supprt 16 MBit falsh such as MX25L12835FM2I(SOP8),MX25L12845EMI(SOP16)
2.how to set overclocking as 500
after those change, how to get the uboot?
Many thanks.

Post #54

pepe2k

18 May 2013, 09:12

Hi!

Davidwei wrote:

Hi,pepe2k
i download your sources code frome http://www.tech-blog.pl/pliki/u-boot_sources_for_tp-link_AR9331_by_pepe2k.tar.gz
but i dont know how to build.

Please, read README file in "toolchain" folder.

Davidwei wrote:

the follwing is my adm
1.make the new uboot supprt 16 MBit falsh such as MX25L12835FM2I(SOP8),MX25L12845EMI(SOP16)

Do you know the JEDEC ID for these chips?

Davidwei wrote:

2.how to set overclocking as 500

All you need to do is just change CFG_PLL_FREQ define value in ap121.h (u-boot/include/configs). I made a setting for this frequency: CFG_PLL_500_250_250.

Davidwei wrote:

after those change, how to get the uboot?

In the top dir just run "make model", where "model" is mr3020, mr3040 etc.

Davidwei wrote:

Many thanks.

You're welcome!

Post #55

alphasparc

18 May 2013, 10:39

Thanks pepe2k!
Succeeded now my MR3020 is running at 500MHZ!
Now I am waiting for your WDR3600/WDR4300 bootloader!

Post #56

pepe2k

18 May 2013, 16:06

alphasparc wrote:

Succeeded now my MR3020 is running at 500MHZ!

Have you made some stability test on these frequencies?

Post #57

alphasparc

19 May 2013, 12:25

I tested everything works at 500MHZ.
Regarding the code

#define CFG_HZ (500000000/2)

// CPU_DIV = 1, RAM_DIV = 2, AHB_DIV = 2
#define CPU_CLK_CONTROL_VAL1 0x00008404
#define CPU_CLK_CONTROL_VAL2 0x00008400

// DIV_INT = 40 (25 MHz * 40/2 = 500 MHz)
// REFDIV = 1
// RANGE = 0
// OUTDIV = 1
#define CPU_PLL_CONFIG_VAL1 0x4081A000
#define CPU_PLL_CONFIG_VAL2 0x0081A000

// CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
#define AR7240_SPI_CONTROL 0x43

Is all the fields required?
I notice that a lot of the defines are not included in the default uboot source.

Post #58

xopal

20 May 2013, 17:48

Tested on my 3220v2 at 562.5 mHz , so far so good , USB works too but data transfer not tested yet.

root@OpenWrt:/# dmesg | grep Clocks:
[    0.000000] Clocks: CPU:562.500MHz, DDR:281.250MHz, AHB:140.625MHz, Ref:25.000MHz
root@OpenWrt:/# cat /proc/cpuinfo
system type             : Atheros AR9330 rev 1
machine                 : TP-LINK TL-MR3220 v2
processor               : 0
cpu model               : MIPS 24Kc V7.4
BogoMIPS                : 373.55
wait instruction        : yes
microsecond timers      : yes
tlb_entries             : 16
extra interrupt vector  : yes
hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000, 0x0610, 0x0310, 0x0210]
ASEs implemented        : mips16
shadow register sets    : 1
kscratch registers      : 0
core                    : 0
VCED exceptions         : not available
VCEI exceptions         : not available

root@OpenWrt:/# dmesg | grep Clocks:
[    0.000000] Clocks: CPU:562.500MHz, DDR:281.250MHz, AHB:140.625MHz, Ref:25.000MHz
root@OpenWrt:/# lsusb
Bus 001 Device 002: ID 08ec:204b M-Systems Flash Disk Pioneers TravelDrive
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Post #59

pepe2k

20 May 2013, 18:00

xopal wrote:

Tested on my 3220v2 at 562.5 mHz , so far so good , USB works too but data transfer not tested yet.

Download "memtester" and "stress" and make some stability tests. After that you should test USB - transfer some huge data using FTP and you will know if these frequencies are stable and... how much did you loose on USB transfer speed

In my opinion, setting DDR and AHB frequencies on this platform lower than default settings (400/200) doesn't make any sens... Higher CPU frequency gives only higher benchmark results. The AHB frequency has bigger impact on USB transfer speed than CPU frequency. So, 562,5 MHz on CPU is just for fun

Post #60

Davidwei

21 May 2013, 12:26

pepe2k wrote:

Hi!
Davidwei wrote:
Hi,pepe2k
i download your sources code frome http://www.tech-blog.pl/pliki/u-boot_sources_for_tp-link_AR9331_by_pepe2k.tar.gz
but i dont know how to build.
Please, read README file in "toolchain" folder.
Davidwei wrote:
the follwing is my adm
1.make the new uboot supprt 16 MBit falsh such as MX25L12835FM2I(SOP8),MX25L12845EMI(SOP16)
Do you know the JEDEC ID for these chips?
Davidwei wrote:
2.how to set overclocking as 500
All you need to do is just change CFG_PLL_FREQ define value in ap121.h (u-boot/include/configs). I made a setting for this frequency: CFG_PLL_500_250_250.
Davidwei wrote:
after those change, how to get the uboot?
In the top dir just run "make model", where "model" is mr3020, mr3040 etc.
Davidwei wrote:
Many thanks.
You're welcome!

Thank you so much! Hoho!
My 740 V5 is running at 500MHZ!
About the JEDEC ID, i don't know how to find. i serch the informaton by google,and just get the manufacturer id&device id.
Does this information is usefull for you? JEDEC ID:1-byte Manufacturer ID&2-byte Device ID

MX25L125845E&MX25L12805D have the same ID
manufacturer id:c2
device id:17

MX25L12855E
manufacturer id:c2
device id:88

Post #61

Davidwei

23 May 2013, 10:50

Davidwei wrote:

pepe2k wrote:
Hi!
Davidwei wrote:
Hi,pepe2k
i download your sources code frome http://www.tech-blog.pl/pliki/u-boot_sources_for_tp-link_AR9331_by_pepe2k.tar.gz
but i dont know how to build.
Please, read README file in "toolchain" folder.
Davidwei wrote:
the follwing is my adm
1.make the new uboot supprt 16 MBit falsh such as MX25L12835FM2I(SOP8),MX25L12845EMI(SOP16)
Do you know the JEDEC ID for these chips?
Davidwei wrote:
2.how to set overclocking as 500
All you need to do is just change CFG_PLL_FREQ define value in ap121.h (u-boot/include/configs). I made a setting for this frequency: CFG_PLL_500_250_250.
Davidwei wrote:
after those change, how to get the uboot?
In the top dir just run "make model", where "model" is mr3020, mr3040 etc.
Davidwei wrote:
Many thanks.
You're welcome!
Thank you so much! Hoho!
My 740 V5 is running at 500MHZ!
About the JEDEC ID, i don't know how to find. i serch the informaton by google,and just get the manufacturer id&device id.
Does this information is usefull for you? JEDEC ID:1-byte Manufacturer ID&2-byte Device ID
MX25L125845E&MX25L12805D have the same ID
manufacturer id:c2
device id:17
MX25L12855E
manufacturer id:c2
device id:88

Post #62

pepe2k

23 May 2013, 10:53

I'm very busy now, so this project is currently on hold.

Post #63

fjorger

9 Jun 2013, 01:09

Hi pepe2K,

I'm sorry to bother you (you said you are quite busy). So I'm not asking for an update status on the project.

Instead I'm going to ask if you can please send us the (beta versions) of UBoot for 3600/4300/4900, allowing people with flash programmers to try them out?

BTW: what type of flash size will be possible on the 3600/4300? 16MB only? Or something like 32MB or even 64MB?

Thanks in advance,

Best regards,

fjorger.

Post #64

fr4nk

9 Jun 2013, 19:51

@pepe2k

I have a wr741nd v4 can I use wr740n bootloader?

Post #65

pepe2k

9 Jun 2013, 20:06

fjorger wrote:

Instead I'm going to ask if you can please send us the (beta versions) of UBoot for 3600/4300/4900, allowing people with flash programmers to try them out?

I don't have any beta version, I will publish only the final version.
It won't work on WDR4900, because it has different SoC.

fjorger wrote:

BTW: what type of flash size will be possible on the 3600/4300? 16MB only? Or something like 32MB or even 64MB?

I don't know and I didn't try 32 MB but probably 16 MB in single chip is the maximum for this SoC.
If you have access to 32 MB chips check if you can use all space on it.

fr4nk wrote:

I have a wr741nd v4 can I use wr740n bootloader?

Yes, at least if your model has AR9331 SoC. Let me know if it works.

Post #66

fjorger

10 Jun 2013, 00:15

pepe2k wrote:

fjorger wrote:
Instead I'm going to ask if you can please send us the (beta versions) of UBoot for 3600/4300/4900, allowing people with flash programmers to try them out?
I don't have any beta version, I will publish only the final version.
It won't work on WDR4900, because it has different SoC.
fjorger wrote:
BTW: what type of flash size will be possible on the 3600/4300? 16MB only? Or something like 32MB or even 64MB?
I don't know and I didn't try 32 MB but probably 16 MB in single chip is the maximum for this SoC.
If you have access to 32 MB chips check if you can use all space on it.

Thanks for your quick reply

Please keep us posted about new uboots for the 3600/4300.
About 32MB chips, I'm still looking/investigating, and I will use my friends flash programmer to try it out.
I will post the results here.

Best regards,
fjorger.

Post #67

fuchenkai

11 Jun 2013, 04:15

great job! i translate the html to chinese and overclock to 500_500_250. it can run at most devices（some RAM can't run at 500MHz）

Post #68

fuchenkai

11 Jun 2013, 04:17

fr4nk wrote:

@pepe2k
I have a wr741nd v4 can I use wr740n bootloader?

of course! same as wr740v4.

Post #69

fr4nk

11 Jun 2013, 16:31

Thanks pepe2k, I can confirm this is working on Wr741ND Version 4.20, tested 425/425/212.

@fuchenkai

What are the options for 500/500/250?

Post #70

pepe2k

12 Jun 2013, 20:51

Just a small but very important notice: I found a bug in my project. So, if you want to use it, please wait for the next release which I'm going to publish in next days.

In very rare cases (2 from 20 different routers) this bug may result in silent crash the U-Boot at PLL register setting stage (so it won't boot and a hardware reset is needed). This bug is not critical - it doesn't occur every time.

It took me couple of days to discover the reason and then test the solution.

Post #71

fjorger

12 Jun 2013, 23:40

pepe2k wrote:

Just a small but very important notice: I found a bug in my project. So, if you want to use it, please wait for the next release which I'm going to publish in next days.

Sorry for asking again.

I know my question is kind of obvious, but you are not talking about 3600/4300 release?
That is still very far away, right?

Thanks.

Regards,

fjorger.

(Last edited by fjorger on 12 Jun 2013, 23:41)

Post #72

pepe2k

12 Jun 2013, 23:49

fjorger wrote:

I know my question is kind of obvious, but you are not talking about 3600/4300 release?

No, I'm talking about release updated version of this project - U-Boot modification for TP-Link with AR9331 SoC.

fjorger wrote:

That is still very far away, right?

No, I have working version but it still needs some work.
My U-Boot modification for WDR3600/4300 won't be included in this project.

Post #73

fjorger

13 Jun 2013, 00:15

Hello pepe2k.

Thanks for the lighting speed reply

And sorry for being so pushy

Regards,

fjorger.

Post #74

sevikcla

13 Jun 2013, 14:38

Hi pepe2k!
I just installed your modified U-boot version on a WLM113 module, which should be almost identically to wr703n, according to the manufacturers. It works great except for the WIFI, when I run wifi from the cmd prompt I get

root@OpenWrt:~# wifi
Configuration file: /var/run/hostapd-phy0.conf
Could not set interface wlan0 flags (UP): Cannot assign requested address
nl80211: Could not set interface 'wlan0' UP
nl80211 driver initialization failed.
Failed to start hostapd for phy0

I have also tested the MR3020 version of the uboot and openwrt. Same issue.

Since I'm a novice on openwrt it would be great if you could point me in the right direction on how to solve this.

Console dump

*****************************************
*      U-Boot 1.1.4  (Apr 22 2013)      *
*****************************************

AP121 (AR9331) U-Boot for TL-MR3020

DRAM:  32 MB
FLASH: Macronix MX25L320 (4 MB)

LED on during eth initialization...

## Error: MAC address stored in flash is invalid!
Using fixed address!
## Error: MAC address stored in flash is invalid!
Using fixed address!
Hit any key to stop autobooting:  0

Booting image at: 0x9F020000...
Uncompressing kernel image...
OK
Starting kernel...

[    0.000000] Linux version 3.3.8 (x@Ubuntu) (gcc version 4.6.4 20121001 (prerelease) (Linaro GCC 4.6-2012.10) ) #25 Thu Jun 13 12:32:06 CEST 2013
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU revision is: 00019374 (MIPS 24Kc)
[    0.000000] SoC: Atheros AR9330 rev 1
[    0.000000] Clocks: CPU:400.000MHz, DDR:400.000MHz, AHB:200.000MHz, Ref:25.000MHz
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 02000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Zone PFN ranges:
[    0.000000]   Normal   0x00000000 -> 0x00002000
[    0.000000] Movable zone start PFN for each node
[    0.000000] Early memory PFN ranges
[    0.000000]     0: 0x00000000 -> 0x00002000
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8128
[    0.000000] Kernel command line:  board=TL-WR703N console=ttyATH0,115200 rootfstype=squashfs,jffs2 noinitrd
[    0.000000] PID hash table entries: 128 (order: -3, 512 bytes)
[    0.000000] Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000000] Primary instruction cache 64kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes
[    0.000000] Writing ErrCtl register=00000000
[    0.000000] Readback ErrCtl register=00000000
[    0.000000] Memory: 29156k/32768k available (2084k kernel code, 3612k reserved, 397k data, 208k init, 0k highmem)
[    0.000000] SLUB: Genslabs=9, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[    0.000000] NR_IRQS:51
[    0.000000] Calibrating delay loop... 265.42 BogoMIPS (lpj=1327104)
[    0.080000] pid_max: default: 32768 minimum: 301
[    0.080000] Mount-cache hash table entries: 512
[    0.090000] NET: Registered protocol family 16
[    0.090000] gpiochip_add: registered GPIOs 0 to 29 on device: ath79
[    0.100000] MIPS: machine is TP-LINK TL-WR703N v1
[    0.350000] bio: create slab <bio-0> at 0
[    0.360000] Switching to clocksource MIPS
[    0.360000] NET: Registered protocol family 2
[    0.370000] IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.370000] TCP established hash table entries: 1024 (order: 1, 8192 bytes)
[    0.370000] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[    0.380000] TCP: Hash tables configured (established 1024 bind 1024)
[    0.390000] TCP reno registered
[    0.390000] UDP hash table entries: 256 (order: 0, 4096 bytes)
[    0.400000] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[    0.400000] NET: Registered protocol family 1
[    0.430000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.430000] JFFS2 version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[    0.440000] msgmni has been set to 56
[    0.440000] io scheduler noop registered
[    0.450000] io scheduler deadline registered (default)
[    0.450000] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[    0.460000] ar933x-uart: ttyATH0 at MMIO 0x18020000 (irq = 11) is a AR933X UART
[    0.460000] console [ttyATH0] enabled, bootconsole disabled
[    0.460000] console [ttyATH0] enabled, bootconsole disabled
[    0.480000] m25p80 spi0.0: found mx25l3205d, expected m25p80
[    0.480000] m25p80 spi0.0: mx25l3205d (4096 Kbytes)
[    0.490000] 5 tp-link partitions found on MTD device spi0.0
[    0.490000] Creating 5 MTD partitions on "spi0.0":
[    0.500000] 0x000000000000-0x000000020000 : "u-boot"
[    0.510000] 0x000000020000-0x0000000fe404 : "kernel"
[    0.510000] mtd: partition "kernel" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
[    0.520000] 0x0000000fe404-0x0000003f0000 : "rootfs"
[    0.530000] mtd: partition "rootfs" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
[    0.540000] mtd: partition "rootfs" set to be root filesystem
[    0.550000] mtd: partition "rootfs_data" created automatically, ofs=370000, len=80000
[    0.550000] 0x000000370000-0x0000003f0000 : "rootfs_data"
[    0.560000] 0x0000003f0000-0x000000400000 : "art"
[    0.570000] 0x000000020000-0x0000003f0000 : "firmware"
[    0.590000] ag71xx_mdio: probed
[    0.590000] eth0: Atheros AG71xx at 0xb9000000, irq 4
[    1.150000] ag71xx ag71xx.0: eth0: connected to PHY at ag71xx-mdio.1:04 [uid=004dd041, driver=Generic PHY]
[    1.160000] TCP cubic registered
[    1.160000] NET: Registered protocol family 17
[    1.160000] 8021q: 802.1Q VLAN Support v1.8
[    1.170000] VFS: Mounted root (squashfs filesystem) readonly on device 31:2.
[    1.180000] Freeing unused kernel memory: 208k freed
- preinit -
Press the [f] key and hit [enter] to enter failsafe mode
- regular preinit -
[    6.560000] JFFS2 notice: (404) jffs2_build_xattr_subsystem: complete building xattr subsystem, 1 of xdatum (0 unchecked, 0 orphan) and 12 of xref (0 dead, 2 orphan) found.
switching to jffs2
- init -

Please press Enter to activate this console. [    8.390000] Compat-drivers backport release: compat-drivers-2012-09-04-2-gddac993
[    8.390000] Backport based on wireless-testing.git master-2012-09-07
[    8.400000] compat.git: wireless-testing.git
[    8.430000] cfg80211: Calling CRDA to update world regulatory domain
[    8.440000] cfg80211: World regulatory domain updated:
[    8.440000] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[    8.450000] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    8.460000] cfg80211:   (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[    8.460000] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
[    8.470000] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    8.480000] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    8.720000] SCSI subsystem initialized
[    8.860000] usbcore: registered new interface driver usbfs
[    8.860000] usbcore: registered new interface driver hub
[    8.870000] usbcore: registered new device driver usb
[    9.350000] ieee80211 phy0: Atheros AR9330 Rev:1 mem=0xb8100000, irq=2
[    9.350000] cfg80211: Calling CRDA for country: US
[    9.360000] cfg80211: Regulatory domain changed to country: US
[    9.360000] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
[    9.370000] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2700 mBm)
[    9.380000] cfg80211:   (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 1700 mBm)
[    9.390000] cfg80211:   (5250000 KHz - 5330000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    9.390000] cfg80211:   (5490000 KHz - 5600000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    9.400000] cfg80211:   (5650000 KHz - 5710000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
[    9.410000] cfg80211:   (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 3000 mBm)
[    9.840000] PPP generic driver version 2.4.2
[    9.890000] ip_tables: (C) 2000-2006 Netfilter Core Team
[   10.010000] NET: Registered protocol family 24
[   10.040000] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[   10.050000] ehci-platform ehci-platform: Generic Platform EHCI Controller
[   10.050000] ehci-platform ehci-platform: new USB bus registered, assigned bus number 1
[   10.090000] ehci-platform ehci-platform: irq 3, io mem 0x1b000000
[   10.110000] ehci-platform ehci-platform: USB 2.0 started, EHCI 1.00
[   10.110000] hub 1-0:1.0: USB hub found
[   10.110000] hub 1-0:1.0: 1 port detected
[   10.140000] nf_conntrack version 0.5.0 (458 buckets, 1832 max)

Post #75

fjorger

13 Jun 2013, 18:04

Hi sevikcla,

Did you perform a backup of your art partition?

I guess not.
You need to get an art partition and restore it's wifi calibration data.

Taken from this post https://forum.openwrt.org/viewtopic.php?id=28343 from Dioptimizer

backup u-boot:

    cat /dev/mtd0 > /tmp/backup_u-boot.bin

backup art:

    cat /dev/mtd4 > /tmp/backup_art.bin

buckup firmware with your settings:

    cat /dev/mtd5 > /tmp/backup_firmware.bin

    Note:
    This firmware you can flash through the Web interface or the MTD method!

buckup fullflash:

    cat /dev/mtd0 > /tmp/backup_fullflash.bin
    cat /dev/mtd5 >> /tmp/backup_fullflash.bin
    cat /dev/mtd4 >> /tmp/backup_fullflash.bin

then copy bin file from tmp dir on router in your computer via WinSCP.

Regards,

fjorger.

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