ethaddr is a MAC, not IP...

it's mac address,that's insterset,on other uboot i never need set up them.

http://www.youtube.com/watch?v=IKQ5oh6DoLA here is the video i make.

http://www.youtube.com/watch?v=wKinpn-7Xhs here is mips's uboot test

when the led is not blink,it just trap at boot.

(Last edited by slboat on 17 Jun 2013, 17:04)

I removed ethaddr from U-Boot env in my mod, because I'm using MAC from FLASH which isn't the same for all routers. So it can't be hard coded. Why do you want to change IP? You can just change IP on your PC and use default addresses from my U-Boot

Yes. As I mentioned before, solution will be included in next release. I'm working on it.

that's good,if any test need,plz send to me,i have a lot wr703 can use for test

I have just published new version, marked: Jun 19 2013

Changes:

• fixed problem with booting in some cases on all supported models

• support for TL-MR10U ver. 1.x (tested on ver. 1.0)

• support fot TL-MR3220 ver. 2.x (tested on ver. 2.1)

• support for TL-WR720N ver. 3 (only for Chinese version!)

• support for new flash types/series: Macronix MX25L128 and SST 25VF064C

• version for TL-WR740N v4 was tested also on TL-WR741ND ver. 4.2 (it's almost the same hardware)

This is probably the last release for this project, I think that it's finished. Of course, if you find any bug I will try to fix it and release a solution but for any additional functionalities (like option to change MAC directly from website) you need to ask me privately.

I'm focusing now on AR9344 and AR9341 SoC (U-Boot modification with web server and overclocking options).

(Last edited by pepe2k on 19 Jun 2013, 21:40)

Great news pepe2k! Looking forward for the AR9344/AR9341 project!

Yes,

Great news pepe2k

I'm available to test it.

Regards,

FJorger.

Can it support for TL-MR11U ?

Yes, it supports MR11U. I didn't make special profile for this model because it's almost the same hardware as MR3040 so just upload version for MR3040. I have tested version for MR3040 only on MR3040 v1.

You have two options:
- TFTP in U-Boot (you will need access to UART console)
- from OpenWrt but you will need to build custom image with write enabled on uboot partition

If you need instructions, you can find them in my article (for the TFTP method): http://translate.google.com/translate?h … console%2F

ok, thank you.
i already find how to on your website.
already on your u-boot. thank you.

(Last edited by derrij on 21 Jun 2013, 15:16)

After I test it, I find it does not seem to support the tp-link official firmware. Official firmware can help more easily  connect to Internet via 3G Network in China.

It supports all firmware as long as they don't contain U-Boot. Probably you tried to upload firmware from TP-Link with U-Boot included in image. It won't work - you need to extract only the firmware from this kind of image. Only official firmware supports upgrade with image which contains U-Boot.

Thanks you!
I will do more try.

I added info about pepe2k's U-Boot mod to following wiki pages:

http://wiki.openwrt.org/toh/tp-link/tl-mr11u#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-mr3020#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-mr3040#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-mr3420#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-wr703n#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-wr720n#bootloader.mods
http://wiki.openwrt.org/toh/tp-link/tl-wr740n#bootloader.mods

Don't mean to be rude, but why use uboot 1.1.4?

As you can see here: ftp://ftp.denx.de/pub/u-boot/ it's from 2005. (See also http://www.denx.de/wiki/U-Boot/ReleaseCycle)

Why not base it on say u-boot-2013.04?

You should ask about this developers from TP-Link, not me. My modification is based on official TP-Link sources and they are using 1.1.4 version for all (or almost all) routers.

Why change something which works OK? Is something wrong with version 1.1.4?

I know that it is very old version, but I don't have time to move code into the newest version. Effort for this won't worth the results.

U-Boot is responsible only for hardware initialization and kernel start... so as long as it works, we don't need any new version. Probably, the same thoughts have developers from TP-Link

hello，pepe2k,

I write the uboot for tl-wr703n into WR11U by mistake. But the WR11U works fine.
So what is the difference between the uboot for tl-wr703n and the uboot for tl-mr3040?

For all supported devices the only differences are GPIO numbers for LEDs, reset button and model name in bootlog. Other elements are the same (hardware initialization - PLL, network and so on). You can dive into sources and check Makefiles where I defined different devices.

In rare case there could be a problem if you upload wrong version which try to enable/disable GPIO which isn't connected to LED or button but... for example control power supply for DRAM chip, USB etc.

So, before anyone upload wrong version (for example to new device based on AR9331 which isn't officially supported in my modification), please check the GPIOs numbers and their roles.

All I see is that in contrast to e.g. opkg, uboot and the Linux kernel are being developed further and further and quite a pace. And yes, from time to time, elder hardware does profit from this development. The uboot-version for the Seagate Dockstar can even boot the entire operating system from a ext2-formated USB stick. While most of us probably do not require such a functionality in a bootloader for a small embedded router, I wonder, whether such a functionality would benefit development somehow.

The functionality is already there, for free. Well, almost for free, because for you (and others) to benefit from this ever going development, you would need to stop just forking things without even thinking about mainlining  your work, and then base your work upon this fork even 7 years later. Then hope, that somebody will integrate this or parts of it, into mainline uboot/linux/coreboot/you-name-it

But you are right, it works. It can boot the operating system.

703n uboot can work on 437.5 M,as follows:
[    0.000000] Linux version 3.8.13 (openwrt@john) (gcc version 4.6.4 (OpenWrt/Linaro GCC 4.6-2012.12 r37008) ) #2 Mon Jun 24 00:05:07 CST 2013
[    0.000000] MyLoader: sysp=865098c0, boardp=b1ee4134, parts=868e14b1
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU revision is: 00019374 (MIPS 24Kc)
[    0.000000] SoC: Atheros AR9330 rev 1
[    0.000000] Clocks: CPU:437.500MHz, DDR:437.500MHz, AHB:218.750MHz, Ref:25.000MHz
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 04000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x00000000-0x03ffffff]

[    0.000000] Linux version 3.8.13 (openwrt@john) (gcc version 4.6.4 (OpenWrt/Linaro GCC 4.6-2012.12 r37008) ) #2 Mon Jun 24 00:05:07 CST 2013
[    0.000000] MyLoader: sysp=42e59069, boardp=36e20604, parts=2082ec52
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU revision is: 00019374 (MIPS 24Kc)
[    0.000000] SoC: Atheros AR9330 rev 1
[    0.000000] Clocks: CPU:512.500MHz, DDR:512.500MHz, AHB:256.250MHz, Ref:25.000MHz
[    0.000000] Determined physical RAM map:

You should make a lot of stability test if you want to use this platform on these frequencies... especially, you should run RAM (for example memtester) and USB (transfer data from pendrive over the network) tests.

Patch for 437-500 mhz

Use at you own risk!

Don't use this if you have no hardware flasher!

--- u-boot/include/configs/ap121.h.orig    2013-06-12 21:39:45.000000000 +0200
+++ u-boot/include/configs/ap121.h    2013-06-27 01:29:12.276349858 +0200
@@ -182,7 +182,117 @@
 
     // CLOCK_DIVIDER = 2 (SPI clock = 212,5 / 6 ~ 35,4 MHz)
     #define AR7240_SPI_CONTROL        0x42
+    
+#elif (CFG_PLL_FREQ == CFG_PLL_437_437_218)
 
+    #define CFG_HZ                    (437500000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 35    (25 MHz * 35/2 = 437,5 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x40818C00
+    #define CPU_PLL_CONFIG_VAL2        0x00818C00
+
+    // CLOCK_DIVIDER = 2 (SPI clock = 218,75 / 6 ~ 36,5 MHz)
+    #define AR7240_SPI_CONTROL        0x42    
+
+
+#elif (CFG_PLL_FREQ == CFG_PLL_450_450_225)
+
+    #define CFG_HZ                    (450000000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 36    (25 MHz * 36/2 = 450 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x40819000
+    #define CPU_PLL_CONFIG_VAL2        0x00819000
+
+    // CLOCK_DIVIDER = 3 (SPI clock = 225 / 6 ~ 37,5 MHz)
+    #define AR7240_SPI_CONTROL        0x42
+    
+#elif (CFG_PLL_FREQ == CFG_PLL_462_462_231)
+
+    #define CFG_HZ                    (462500000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 37    (25 MHz * 37/2 = 462,5 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x40819400
+    #define CPU_PLL_CONFIG_VAL2        0x00819400
+
+    // CLOCK_DIVIDER = 3 (SPI clock = 231,25 / 6 ~ 38,5 MHz)
+    #define AR7240_SPI_CONTROL        0x42
+    
+#elif (CFG_PLL_FREQ == CFG_PLL_475_475_237)
+
+    #define CFG_HZ                    (475000000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 38    (25 MHz * 38/2 = 475 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x40819800
+    #define CPU_PLL_CONFIG_VAL2        0x00819800
+
+    // CLOCK_DIVIDER = 3 (SPI clock = 237,5 / 6 ~ 39,6 MHz)
+    #define AR7240_SPI_CONTROL        0x42    
+    
+#elif (CFG_PLL_FREQ == CFG_PLL_487_487_243)
+
+    #define CFG_HZ                    (487500000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 39    (25 MHz * 39/2 = 487,5 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x40819C00
+    #define CPU_PLL_CONFIG_VAL2        0x00819C00
+
+    // CLOCK_DIVIDER = 3 (SPI clock = 243,75 / 8 ~ 30,5 MHz)
+    #define AR7240_SPI_CONTROL        0x43    
+    
+
+#elif (CFG_PLL_FREQ == CFG_PLL_500_500_250)
+
+    #define CFG_HZ                    (500000000/2)
+
+    // CPU_DIV = 1, RAM_DIV = 1, AHB_DIV = 2
+    #define CPU_CLK_CONTROL_VAL1    0x00018004
+    #define CPU_CLK_CONTROL_VAL2    0x00008000
+
+    // DIV_INT    = 40    (25 MHz * 40/2 = 500 MHz)
+    // REFDIV    = 1
+    // RANGE    = 0
+    // OUTDIV    = 1
+    #define CPU_PLL_CONFIG_VAL1        0x4081A000
+    #define CPU_PLL_CONFIG_VAL2        0x0081A000
+
+    // CLOCK_DIVIDER = 3 (SPI clock = 250 / 8 ~ 31,3 MHz)
+    #define AR7240_SPI_CONTROL        0x43
+    
 #elif (CFG_PLL_FREQ == CFG_PLL_500_250_250)
 
     #define CFG_HZ                    (500000000/2)

pepe2k,

Do you have any variables of FLASH SIZE defined in your code, so that I can compile you uboot for my hardware mod.

I want to replace factory 4M flash chip to 16M so that I have to re-compile your uboot code.

thanks.