OpenWrt Forum Archive

Topic: Netgear R8000 support?

The content of this topic has been archived between 23 Mar 2018 and 5 May 2018. Unfortunately there are posts – most likely complete pages – missing.

Right, but the confusing this is that Luxul XWC-1000 has core rev 0x05 and it still works OK.

So maybe it's switch chipset that makes the difference? Maybe we don't support anything other than BCM53011 rev 3? This would require comparing b53 with bcmrobo.c in Broadcom's sources.

I can already say that there is likely something wrong with b53 because PHY requires a hack, see 900-bgmac-some-fixes-to-get-bgmac-work.patch
I was trying to fix it (using Netgear R6250), but didn't find the solution sad

Zajec wrote:

Right, but the confusing this is that Luxul XWC-1000 has core rev 0x05 and it still works OK.

So maybe it's switch chipset that makes the difference? Maybe we don't support anything other than BCM53011 rev 3? This would require comparing b53 with bcmrobo.c in Broadcom's sources.

I can already say that there is likely something wrong with b53 because PHY requires a hack, see 900-bgmac-some-fixes-to-get-bgmac-work.patch
I was trying to fix it (using Netgear R6250), but didn't find the solution sad

Yes, that's what I was trying to say above, Luxul XWC-1000 does have switch rev 3 and the problem devices have rev 5.
I also don't believe the problem is related to hardware changes from core rev 4 to 5.

The information you posted above was what I was looking for as evidence of this, and pointing me to the b53 code (that I've been avoiding) is definitely good advice.

Here is dmesg output from enabling the wireless.
I created /etc/config/wireless using wifi detect and then altered it to use "option hwmode   11a" and "option htmode   VHT20" for devices 2 and three.
If I leave the devices at 11g the interfaces do get created.

root@OpenWrt:/# dmesg
[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.18.9 (raven@perseus.themaw.net) (gcc version 4.8.3 (OpenWrt/Linaro GCC 4.8-2014.04 r44621) ) #1 SMP Wed Mar 25 16:31:25 AWST 2015
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine model: Netgear R8000 (BCM4709)
[    0.000000] bootconsole [earlycon0] enabled
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] On node 0 totalpages: 65536
[    0.000000] free_area_init_node: node 0, pgdat c03d5640, node_mem_map c6df8000
[    0.000000]   Normal zone: 256 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 32768 pages, LIFO batch:7
[    0.000000]   HighMem zone: 4352 pages used for memmap
[    0.000000]   HighMem zone: 32768 pages, LIFO batch:7
[    0.000000] PERCPU: Embedded 9 pages/cpu @c6dd5000 s5952 r8192 d22720 u36864
[    0.000000] pcpu-alloc: s5952 r8192 d22720 u36864 alloc=9*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65280
[    0.000000] Kernel command line: console=ttyS0,115200 earlyprintk
[    0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Memory: 255552K/262144K available (2898K kernel code, 107K rwdata, 792K rodata, 180K init, 276K bss, 6592K reserved, 131072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xffe00000   (2048 kB)
[    0.000000]     vmalloc : 0xc8800000 - 0xff000000   ( 872 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xc8000000   ( 128 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc03a2dcc   (3692 kB)
[    0.000000]       .init : 0xc03a3000 - 0xc03d0000   ( 180 kB)
[    0.000000]       .data : 0xc03d0000 - 0xc03eac88   ( 108 kB)
[    0.000000]        .bss : 0xc03eac88 - 0xc042fdd4   ( 277 kB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: platform modifies aux control register: 0x0a130000 -> 0x7a130000
[    0.000000] L2C: platform provided aux values permit register corruption.
[    0.000000] L2C: DT/platform modifies aux control register: 0x0a130000 -> 0x7a130000
[    0.000000] L2C-310 erratum 769419 enabled
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 1 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 16 ways, 256 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x7e130001
[    0.000015] sched_clock: 64 bits at 400MHz, resolution 2ns, wraps every 2748779069440ns
[    0.010425] Calibrating delay loop... 1594.16 BogoMIPS (lpj=7970816)
[    0.103844] pid_max: default: 32768 minimum: 301
[    0.109881] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.118282] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.127729] CPU: Testing write buffer coherency: ok
[    0.134198] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.141519] Setting up static identity map for 0x11a50 - 0x11a84
[    0.150989] CPU1: Booted secondary processor
[    0.190232] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.190310] Brought up 2 CPUs
[    0.206791] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[    0.214869] CPU: All CPU(s) started in SVC mode.
[    0.227935] NET: Registered protocol family 16
[    0.234361] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.272450] Switched to clocksource arm_global_timer
[    0.279924] NET: Registered protocol family 2
[    0.286251] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[    0.295126] TCP bind hash table entries: 1024 (order: 1, 8192 bytes)
[    0.303231] TCP: Hash tables configured (established 1024 bind 1024)
[    0.311362] TCP: reno registered
[    0.315520] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    0.322967] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    0.331184] NET: Registered protocol family 1
[    0.336802] PCI: CLS 0 bytes, default 64
[    0.337762] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.346508] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.353972] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[    0.366527] msgmni has been set to 243
[    0.371872] bounce: pool size: 64 pages
[    0.376796] io scheduler noop registered
[    0.381857] io scheduler deadline registered (default)
[    0.388751] Serial: 8250/16550 driver, 16 ports, IRQ sharing enabled
[    0.399027] console [ttyS0] disabled
[    0.403682] 18000300.serial: ttyS0 at MMIO 0x18000300 (irq = 117, base_baud = 7812500) is a 16550
[    0.414932] console [ttyS0] enabled
[    0.423784] bootconsole [earlycon0] disabled
[    0.434927] 18000400.serial: ttyS1 at MMIO 0x18000400 (irq = 117, base_baud = 7812500) is a 16550
[    0.447546] libphy: Fixed MDIO Bus: probed
[    0.452792] bgmac: Broadcom 47xx GBit MAC driver loaded
[    0.459541] bcma: bus0: Found chip with id 53010, rev 0x00 and package 0x00
[    0.468345] bcma: bus0: Core 0 found: ChipCommon (manuf 0x4BF, id 0x800, rev 0x2A, class 0x0)
[    0.479117] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.479130] bcma: bus0: Core 1 found: Chipcommon B (manuf 0x4BF, id 0x50B, rev 0x01, class 0x0)
[    0.490110] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.490123] bcma: bus0: Core 2 found: DMA (manuf 0x4BF, id 0x502, rev 0x01, class 0x0)
[    0.500113] bcma: bus0: Core 3 found: GBit MAC (manuf 0x4BF, id 0x82D, rev 0x05, class 0x0)
[    0.510643] bcma: bus0: Core 4 found: GBit MAC (manuf 0x4BF, id 0x82D, rev 0x05, class 0x0)
[    0.521187] bcma: bus0: Core 5 found: GBit MAC (manuf 0x4BF, id 0x82D, rev 0x05, class 0x0)
[    0.531720] bcma: bus0: Core 6 found: GBit MAC (manuf 0x4BF, id 0x82D, rev 0x05, class 0x0)
[    0.542218] bcma: bus0: Core 7 found: PCIe Gen 2 (manuf 0x4BF, id 0x501, rev 0x01, class 0x0)
[    0.552943] bcma: bus0: Core 8 found: PCIe Gen 2 (manuf 0x4BF, id 0x501, rev 0x01, class 0x0)
[    0.563689] bcma: bus0: Core 9 found: PCIe Gen 2 (manuf 0x4BF, id 0x501, rev 0x01, class 0x0)
[    0.574452] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.574464] bcma: bus0: Core 10 found: ARM Cortex A9 core (ihost) (manuf 0x4BF, id 0x510, rev 0x01, class 0x0)
[    0.587058] bcma: bus0: Core 11 found: USB 2.0 (manuf 0x4BF, id 0x504, rev 0x01, class 0x0)
[    0.597592] bcma: bus0: Core 12 found: USB 3.0 (manuf 0x4BF, id 0x505, rev 0x01, class 0x0)
[    0.608134] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.608147] bcma: bus0: Core 13 found: SDIO3 (manuf 0x4BF, id 0x503, rev 0x01, class 0x0)
[    0.618469] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.618482] bcma: bus0: Core 14 found: I2S (manuf 0x4BF, id 0x834, rev 0x03, class 0x0)
[    0.628588] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.628601] bcma: bus0: Core 15 found: ARM Cortex A9 JTAG (manuf 0x4BF, id 0x506, rev 0x01, class 0x0)
[    0.640338] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.640351] bcma: bus0: Core 16 found: Denali DDR2/DDR3 memory controller (manuf 0x4BF, id 0x507, rev 0x01, class 0x0)
[    0.653839] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.653851] bcma: bus0: Core 17 found: ROM (manuf 0x4BF, id 0x508, rev 0x01, class 0x0)
[    0.663958] bcma: bus0: Core 18 found: NAND flash controller (manuf 0x4BF, id 0x509, rev 0x01, class 0x0)
[    0.676028] bcma: bus0: bcma_of_get_irq() failed with rc=-22
[    0.676040] bcma: bus0: Core 19 found: SPI flash controller (manuf 0x4BF, id 0x50A, rev 0x01, class 0x0)
[    0.700271] bcm_nand bcma0:18: NAND Controller rev 6.01
[    0.730304] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xf1
[    0.738268] nand: Macronix NAND 128MiB 3,3V 8-bit
[    0.744179] nand: 128MiB, SLC, page size: 2048, OOB size: 64
[    0.849224] mtd_read error while parsing (offset: 0x880000)!
[    1.104588] mtd_read error while parsing (offset: 0x1DC0000)!
[    1.286308] mtd_read error while parsing (offset: 0x2D00000)!
[    2.004195] random: nonblocking pool is initialized
[    2.301722] 17 bcm47xxpart partitions found on MTD device bcm_nand
[    2.309471] Creating 17 MTD partitions on "bcm_nand":
[    2.315817] 0x000000000000-0x000000080000 : "boot"
[    2.323726] 0x000000080000-0x000000200000 : "nvram"
[    2.333978] 0x000000200000-0x000002600000 : "firmware"
[    2.422836] 0x00000020001c-0x000000360000 : "linux"
[    2.428957] mtd: partition "linux" must either start or end on erase block boundary or be smaller than an erase block -- forcing read-only
[    2.448378] 0x000000360000-0x000002600000 : "ubi"
[    2.533564] 0x000002600000-0x000002680000 : "board_data"
[    2.542088] 0x000002680000-0x0000026a0000 : "POT"
[    2.548965] 0x0000026a0000-0x000002780000 : "POT"
[    2.557607] 0x000002780000-0x0000027a0000 : "POT"
[    2.564560] 0x0000027a0000-0x000002e00000 : "POT"
[    2.585602] 0x000002e00000-0x000002e80000 : "ML"
[    2.593237] 0x000002e80000-0x000002f00000 : "ML"
[    2.600891] 0x000002f00000-0x000002f80000 : "ML"
[    2.608516] 0x000002f80000-0x000003000000 : "ML"
[    2.616189] 0x000003000000-0x000003080000 : "ML"
[    2.623847] 0x000003080000-0x000003100000 : "ML"
[    2.631523] 0x000003100000-0x000008000000 : "ML"
[    2.818878] bcm53xxspiflash spi32766.0: unrecognized JEDEC id bytes: ff, ff, ff
[    2.828080] bcm53xxspiflash: probe of spi32766.0 failed with error -2
[    2.844359] bcma: bus0: Using SPROM revision 11 provided by platform.
[    2.844627] bgmac bcma0:3: Found PHY addr: 30 (NOREGS)
[    2.853207] bgmac bcma0:3: Support for Roboswitch not implemented
[    2.862610] b53_common: found switch: BCM53012, rev 5
[    2.869724] bgmac bcma0:4: Found PHY addr: 30 (NOREGS)
[    2.878317] bgmac bcma0:4: Support for Roboswitch not implemented
[    2.887091] bgmac: Unsupported core_unit 2
[    2.892271] bgmac: probe of bcma0:5 failed with error -524
[    2.899239] bgmac: Unsupported core_unit 3
[    2.904395] bgmac: probe of bcma0:6 failed with error -524
[    2.911382] pci_host_bcm5301x bcma0:7: initializing PCIe controller
[    3.190258] pci_host_bcm5301x bcma0:7: link: UP
[    3.196065] pci_host_bcm5301x bcma0:7: PCI host bridge to bus 0000:00
[    3.204160] pci_bus 0000:00: root bus resource [mem 0x08000000-0x0fffffff]
[    3.212784] pci_bus 0000:00: root bus resource [io  0x0000]
[    3.219770] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
[    3.229726] pci 0000:00:00.0: [14e4:8012] type 01 class 0x020000
[    3.229788] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[    3.229986] PCI: bus0: Fast back to back transfers disabled
[    3.237132] pci 0000:01:00.0: [14e4:aa52] type 00 class 0x028000
[    3.237174] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
[    3.237199] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x003fffff 64bit]
[    3.237302] pci 0000:01:00.0: supports D1 D2
[    3.237491] PCI: bus1: Fast back to back transfers disabled
[    3.244500] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[    3.244519] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 01
[    3.244623] pci 0000:00:00.0: BAR 8: assigned [mem 0x08000000-0x085fffff]
[    3.253150] pci 0000:01:00.0: BAR 2: assigned [mem 0x08000000-0x083fffff 64bit]
[    3.262332] pci 0000:01:00.0: BAR 0: assigned [mem 0x08400000-0x08407fff 64bit]
[    3.271513] pci 0000:00:00.0: PCI bridge to [bus 01]
[    3.277741] pci 0000:00:00.0:   bridge window [mem 0x08000000-0x085fffff]
[    3.286410] pci_host_bcm5301x bcma0:8: initializing PCIe controller
[    3.570253] pci_host_bcm5301x bcma0:8: link: UP
[    3.576063] pci_host_bcm5301x bcma0:8: PCI host bridge to bus 0001:00
[    3.584162] pci_bus 0001:00: root bus resource [mem 0x40000000-0x47ffffff]
[    3.592790] pci_bus 0001:00: root bus resource [io  0x0000]
[    3.599777] pci_bus 0001:00: No busn resource found for root bus, will use [bus 00-ff]
[    3.609733] pci 0001:00:00.0: [14e4:8012] type 01 class 0x020000
[    3.609790] pci 0001:00:00.0: PME# supported from D0 D3hot D3cold
[    3.609990] PCI: bus0: Fast back to back transfers disabled
[    3.617145] pci 0001:01:00.0: [10b5:8603] type 01 class 0x060400
[    3.667073] pci 0001:01:00.0: reg 0x10: [mem 0x00000000-0x00003fff]
[    3.667213] pci 0001:01:00.0: supports D1 D2
[    3.667225] pci 0001:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    3.667418] PCI: bus1: Fast back to back transfers disabled
[    3.674619] pci 0001:02:01.0: [10b5:8603] type 01 class 0x060400
[    3.724672] pci 0001:02:01.0: supports D1 D2
[    3.724686] pci 0001:02:01.0: PME# supported from D0 D1 D2 D3hot D3cold
[    3.724890] pci 0001:02:02.0: [10b5:8603] type 01 class 0x060400
[    3.774933] pci 0001:02:02.0: supports D1 D2
[    3.774946] pci 0001:02:02.0: PME# supported from D0 D1 D2 D3hot D3cold
[    3.775160] PCI: bus2: Fast back to back transfers disabled
[    3.782384] pci 0001:03:00.0: [14e4:aa52] type 00 class 0x028000
[    3.782440] pci 0001:03:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
[    3.782474] pci 0001:03:00.0: reg 0x18: [mem 0x00000000-0x003fffff 64bit]
[    3.782649] pci 0001:03:00.0: supports D1 D2
[    3.782856] PCI: bus3: Fast back to back transfers disabled
[    3.797537] pci_bus 0001:04: busn_res: [bus 04-ff] end is updated to 04
[    3.797557] pci_bus 0001:02: busn_res: [bus 02-ff] end is updated to 04
[    3.797575] pci_bus 0001:01: busn_res: [bus 01-ff] end is updated to 04
[    3.797591] pci_bus 0001:00: busn_res: [bus 00-ff] end is updated to 04
[    3.797910] pci 0001:00:00.0: BAR 8: assigned [mem 0x40000000-0x40cfffff]
[    3.806442] pci 0001:00:00.0: BAR 9: assigned [mem 0x40d00000-0x40efffff 64bit pref]
[    3.816162] pci 0001:01:00.0: BAR 8: assigned [mem 0x40000000-0x40bfffff]
[    3.824677] pci 0001:01:00.0: BAR 9: assigned [mem 0x40d00000-0x40efffff 64bit pref]
[    3.834398] pci 0001:01:00.0: BAR 0: assigned [mem 0x40c00000-0x40c03fff]
[    3.842916] pci 0001:01:00.0: BAR 7: no space for [io  size 0x1000]
[    3.850774] pci 0001:01:00.0: BAR 7: failed to assign [io  size 0x1000]
[    3.859063] pci 0001:02:01.0: BAR 8: assigned [mem 0x40000000-0x405fffff]
[    3.867587] pci 0001:02:02.0: BAR 8: assigned [mem 0x40600000-0x40bfffff]
[    3.876108] pci 0001:02:01.0: BAR 9: assigned [mem 0x40d00000-0x40efffff 64bit pref]
[    3.885824] pci 0001:02:01.0: BAR 7: no space for [io  size 0x1000]
[    3.893684] pci 0001:02:01.0: BAR 7: failed to assign [io  size 0x1000]
[    3.901982] pci 0001:03:00.0: BAR 2: assigned [mem 0x40000000-0x403fffff 64bit]
[    3.911170] pci 0001:03:00.0: BAR 0: assigned [mem 0x40400000-0x40407fff 64bit]
[    3.920360] pci 0001:02:01.0: PCI bridge to [bus 03]
[    3.926585] pci 0001:02:01.0:   bridge window [mem 0x40000000-0x405fffff]
[    3.935098] pci 0001:02:01.0:   bridge window [mem 0x40d00000-0x40efffff 64bit pref]
[    3.944820] pci 0001:04:00.0: BAR 2: assigned [mem 0x40800000-0x40bfffff 64bit]
[    3.954002] pci 0001:04:00.0: BAR 0: assigned [mem 0x40600000-0x40607fff 64bit]
[    3.963187] pci 0001:02:02.0: PCI bridge to [bus 04]
[    3.969418] pci 0001:02:02.0:   bridge window [mem 0x40600000-0x40bfffff]
[    3.977937] pci 0001:01:00.0: PCI bridge to [bus 02-04]
[    3.984495] pci 0001:01:00.0:   bridge window [mem 0x40000000-0x40bfffff]
[    3.993011] pci 0001:01:00.0:   bridge window [mem 0x40d00000-0x40efffff 64bit pref]
[    4.002729] pci 0001:00:00.0: PCI bridge to [bus 01-04]
[    4.009279] pci 0001:00:00.0:   bridge window [mem 0x40000000-0x40cfffff]
[    4.017796] pci 0001:00:00.0:   bridge window [mem 0x40d00000-0x40efffff 64bit pref]
[    4.027720] pci_host_bcm5301x bcma0:9: initializing PCIe controller
[    4.420254] pci_host_bcm5301x bcma0:9: link: DOWN
[    4.427349] bcm47xx-wdt bcm47xx-wdt.0: BCM47xx Watchdog Timer enabled (30 seconds, Software Timer)
[    4.438618] bcma: bus0: Bus registered
[    4.443762] TCP: cubic registered
[    4.447934] NET: Registered protocol family 17
[    4.453609] bridge: automatic filtering via arp/ip/ip6tables has been deprecated. Update your scripts to load br_netfilter if you need this.
[    4.469456] Bridge firewalling registered
[    4.474499] 8021q: 802.1Q VLAN Support v1.8
[    4.479814] Registering SWP/SWPB emulation handler
[    4.488267] UBI: auto-attach mtd4
[    4.492458] UBI: attaching mtd4 to ubi0
[    4.978234] UBI: scanning is finished
[    5.000495] UBI: attached mtd4 (name "ubi", size 34 MiB) to ubi0
[    5.008033] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 126976 bytes
[    5.016553] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 2048
[    5.024954] UBI: VID header offset: 2048 (aligned 2048), data offset: 4096
[    5.033587] UBI: good PEBs: 275, bad PEBs: 2, corrupted PEBs: 0
[    5.041010] UBI: user volume: 2, internal volumes: 1, max. volumes count: 128
[    5.049948] UBI: max/mean erase counter: 3/1, WL threshold: 4096, image sequence number: 677945084
[    5.061183] UBI: available PEBs: 0, total reserved PEBs: 275, PEBs reserved for bad PEB handling: 18
[    5.072684] UBI: background thread "ubi_bgt0d" started, PID 296
[    5.081223] UBI: ubiblock0_0 created from ubi0:0(rootfs)
[    5.087885] ubiblock: device ubiblock0_0 (rootfs) set to be root filesystem
[    5.102953] VFS: Mounted root (squashfs filesystem) readonly on device 254:0.
[    5.112172] Freeing unused kernel memory: 180K (c03a3000 - c03d0000)
[    5.421010] External imprecise Data abort at addr=0xb6f0b005, fsr=0x1c06 ignored.
[    5.757016] init: Console is alive
[    5.761563] init: - watchdog -
[    6.511110] usbcore: registered new interface driver usbfs
[    6.518065] usbcore: registered new interface driver hub
[    6.524841] usbcore: registered new device driver usb
[    6.780470] init: - preinit -
[    8.070280] eth0: Link is Up - 1Gbps/Full - flow control off
[   10.051529] UBIFS: background thread "ubifs_bgt0_1" started, PID 366
[   10.143835] UBIFS: recovery needed
[   10.373518] UBIFS: recovery completed
[   10.378205] UBIFS: mounted UBI device 0, volume 1, name "rootfs_data"
[   10.386295] UBIFS: LEB size: 126976 bytes (124 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
[   10.397761] UBIFS: FS size: 26030080 bytes (24 MiB, 205 LEBs), journal size 1269760 bytes (1 MiB, 10 LEBs)
[   10.409871] UBIFS: reserved for root: 1229465 bytes (1200 KiB)
[   10.417199] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 0213812F-DACE-4D93-B5F9-952B64A66296, small LPT model
[   10.436930] mount_root: switching to jffs2 overlay
[   10.464664] procd: - early -
[   10.468381] procd: - watchdog -
[   11.160530] procd: - ubus -
[   12.191911] procd: - init -
[   17.120937] NET: Registered protocol family 10
[   17.131389] ip6_tables: (C) 2000-2006 Netfilter Core Team
[   17.143233] Netfilter messages via NETLINK v0.30.
[   17.150423] ip_set: protocol 6
[   17.170910] Loading modules backported from Linux version master-2015-03-09-0-g141f155
[   17.180865] Backport generated by backports.git backports-20150129-0-gdd4a670
[   17.191494] ip_tables: (C) 2000-2006 Netfilter Core Team
[   17.203486] nf_conntrack version 0.5.0 (3995 buckets, 15980 max)
[   17.282736] xt_time: kernel timezone is -0000
[   17.295609] cfg80211: Calling CRDA to update world regulatory domain
[   17.303798] cfg80211: World regulatory domain updated:
[   17.310287] cfg80211:  DFS Master region: unset
[   17.315758] cfg80211:   (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time)
[   17.328022] cfg80211:   (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[   17.338073] cfg80211:   (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[   17.348119] cfg80211:   (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A)
[   17.358154] cfg80211:   (5170000 KHz - 5250000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[   17.368196] cfg80211:   (5250000 KHz - 5330000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2000 mBm), (0 s)
[   17.380086] cfg80211:   (5490000 KHz - 5730000 KHz @ 160000 KHz), (N/A, 2000 mBm), (0 s)
[   17.390225] cfg80211:   (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[   17.400268] cfg80211:   (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A)
[   17.428270] PPP generic driver version 2.4.2
[   17.434782] NET: Registered protocol family 24
[   17.454423] Broadcom 43xx driver loaded [ Features: PNL ]
[   17.465522] usbcore: registered new interface driver brcmfmac
[   21.300422] device eth0.1 entered promiscuous mode
[   21.306435] device eth0 entered promiscuous mode
[   21.315060] br-lan: port 1(eth0.1) entered forwarding state
[   21.322179] br-lan: port 1(eth0.1) entered forwarding state
[   22.083375] eth0: Link is Up - 1Gbps/Full - flow control off
[   23.320246] br-lan: port 1(eth0.1) entered forwarding state
[   65.767637] brcmfmac 0000:01:00.0: enabling device (0140 -> 0142)
[   65.890373] brcmfmac 0001:03:00.0: enabling device (0140 -> 0142)
[   66.011245] brcmfmac 0001:04:00.0: enabling device (0140 -> 0142)
[   66.162139] brcmfmac 0000:01:00.0: Direct firmware load for brcm/brcmfmac43602-pcie.txt failed with error -2
[   66.174493] brcmfmac 0000:01:00.0: Falling back to user helper
[   66.191361] firmware brcm!brcmfmac43602-pcie.txt: firmware_loading_store: map pages failed
[   66.742920] brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Mar  3 2015 04:46:51 version 7.35.177.33 (r538052) FWID 01-c8317c80
[   66.767925] brcmfmac: brcmf_cfg80211_reg_notifier: not a ISO3166 code
[   66.904222] brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Mar  3 2015 04:46:51 version 7.35.177.33 (r538052) FWID 01-c8317c80
[   66.931907] brcmfmac: brcmf_cfg80211_reg_notifier: not a ISO3166 code
[   66.944231] brcmfmac: brcmf_c_preinit_dcmds: Firmware version = wl0: Mar  3 2015 04:46:51 version 7.35.177.33 (r538052) FWID 01-c8317c80
[   66.976189] brcmfmac: brcmf_cfg80211_reg_notifier: not a ISO3166 code
[   75.353102] brcmfmac: brcmf_add_if: ERROR: netdev:wlan2 already exists
[   75.361336] brcmfmac: brcmf_add_if: ignore IF event
[   75.370358] device wlan2 entered promiscuous mode
[   75.376372] br-lan: port 2(wlan2) entered forwarding state
[   75.383311] br-lan: port 2(wlan2) entered forwarding state
[   75.442366] brcmfmac: brcmf_add_if: ERROR: netdev:wlan1 already exists
[   75.450554] brcmfmac: brcmf_add_if: ignore IF event
[   75.459807] device wlan1 entered promiscuous mode
[   75.465813] br-lan: port 3(wlan1) entered forwarding state
[   75.472757] br-lan: port 3(wlan1) entered forwarding state
[   75.480170] device wlan2 left promiscuous mode
[   75.485935] br-lan: port 2(wlan2) entered disabled state
[   75.525648] brcmfmac: brcmf_add_if: ERROR: netdev:wlan0 already exists
[   75.533881] brcmfmac: brcmf_add_if: ignore IF event
[   75.542081] device wlan1 left promiscuous mode
[   75.547746] br-lan: port 3(wlan1) entered disabled state
[   76.063226] device wlan0 entered promiscuous mode
[   76.069269] br-lan: port 2(wlan0) entered forwarding state
[   76.076297] br-lan: port 2(wlan0) entered forwarding state
[   76.631234] brcmfmac: brcmf_add_if: ERROR: netdev:wlan0 already exists
[   76.639423] brcmfmac: brcmf_add_if: ignore IF event
[   78.071069] br-lan: port 2(wlan0) entered forwarding state
root@OpenWrt:/# root@OpenWrt:/# iw dev wlan0 info
Interface wlan0
        ifindex 7
        wdev 0x1
        addr 00:90:4c:0d:f4:3e
        ssid OpenWrt
        type AP
        wiphy 0
root@OpenWrt:/# root@OpenWrt:/# iw dev wlan1 info
Interface wlan1
        ifindex 8
        wdev 0x100000001
        addr 00:90:4c:0d:f4:3e
        type managed
        wiphy 1
root@OpenWrt:/# iw dev wlan2 info
Interface wlan2
        ifindex 9
        wdev 0x200000001
        addr 00:90:4c:0d:f4:3e
        type managed
        wiphy 2
root@OpenWrt:/# iw dev wlan0 scan
root@OpenWrt:/# iw dev wlan1 scan
command failed: Network is down (-100)
root@OpenWrt:/# iw dev wlan1 scan
command failed: Network is down (-100)
root@OpenWrt:/#

And the created wireless configuration (with changes above):

config wifi-device  radio0
        option type     mac80211
        option channel  11
        option hwmode   11g
        option path     '18000000.axi/bcma0:7/pci0000:00/0000:00:00.0/0000:01:00.0'
        option htmode   HT20

config wifi-iface
        option device   radio0
        option network  lan
        option mode     ap
        option ssid     OpenWrt
        option encryption none

config wifi-device  radio1
        option type     mac80211
        option channel  11
        option hwmode   11a
        option path     '18000000.axi/bcma0:8/pci0001:00/0001:00:00.0/0001:01:00.0/0001:02:01.0/0001:03:00.0'
        option htmode   VHT20

config wifi-iface
        option device   radio1
        option network  lan
        option mode     ap
        option ssid     OpenWrt
        option encryption none

config wifi-device  radio2
        option type     mac80211
        option channel  11
        option hwmode   11a
        option path     '18000000.axi/bcma0:8/pci0001:00/0001:00:00.0/0001:01:00.0/0001:02:02.0/0001:04:00.0'
        option htmode   VHT20

config wifi-iface
        option device   radio2
        option network  lan
        option mode     ap
        option ssid     OpenWrt
        option encryption none

(Last edited by raven-au on 25 Mar 2015, 14:46)

I just picked up an R8000 this week. Originally I was planning to put DD-WRT on it, but Kong's build apparently still has issues, and I'd really prefer the flexibilty of OpenWRT if I had the choice. So

1) How close have you guys gotten to it working?

2) Anything I can do to help? I'm not much of a coder but I know my Linux pretty well.

RobertRollie wrote:

I just picked up an R8000 this week. Originally I was planning to put DD-WRT on it, but Kong's build apparently still has issues, and I'd really prefer the flexibilty of OpenWRT if I had the choice. So

1) How close have you guys gotten to it working?

2) Anything I can do to help? I'm not much of a coder but I know my Linux pretty well.

The switch is still a problem, it simply doesn't work and nothing I do seems to change that.

The bcrmfmac wireless driver isn't working yet either and won't get any attention from me until the switch is working.

raven-au wrote:

The switch is still a problem, it simply doesn't work and nothing I do seems to change that.

Could you try below patch? It probably will make the switch work.

diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
index e44d194..b6e4339 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
@@ -535,6 +535,27 @@ static int b53_switch_reset(struct b53_device *dev)
                PORT_OVERRIDE_LINK);
     }
 
+    if (is5301x(dev)) {
+        u8 val8;
+
+        b53_read8(dev, B53_CTRL_PAGE, B53_CTRL_PORT0_GMIIPO +
+              dev->sw_dev.cpu_port, &val8);
+
+        val8 |=        (1 << 7) |    /* GMII_SPEED_UP_2G */
+                (1 << 6) |    /* SW_OVERRIDE */
+                (1 << 5) |    /* TXFLOW_CNTL */
+                (1 << 4) |    /* RXFLOW_CNTL */
+                        /* default(2 << 2) SPEED :
+                         * 2b10 1000/2000Mbps
+                         */
+                        /* default(1 << 1) DUPLX_MODE:
+                         * Full Duplex
+                         */
+                (1 << 0);    /* LINK_STS: Link up */
+        b53_write8(dev, B53_CTRL_PAGE, B53_CTRL_PORT0_GMIIPO +
+               dev->sw_dev.cpu_port, val8);
+    }
+
     b53_enable_mib(dev);
 
     return b53_flush_arl(dev);
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index 4899cc4..f7b4224 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -99,6 +99,15 @@
 #define B53_MC_FLOOD_MASK        0x34
 #define B53_IPMC_FLOOD_MASK        0x36
 
+/* Access switch registers through SRAB (Switch Register Access Bridge) */
+#define B53_CTRL_PORT0_GMIIPO        0x58
+#define B53_CTRL_PORT1_GMIIPO        0x59
+#define B53_CTRL_PORT2_GMIIPO        0x5a
+#define B53_CTRL_PORT3_GMIIPO        0x5b
+#define B53_CTRL_PORT4_GMIIPO        0x5c
+#define B53_CTRL_PORT5_GMIIPO        0x5d
+#define B53_CTRL_PORT7_GMIIPO        0x5f
+
 /* Software reset register (8 bit) */
 #define B53_SOFTRESET            0x79
meuleman wrote:
raven-au wrote:

The switch is still a problem, it simply doesn't work and nothing I do seems to change that.

Could you try below patch? It probably will make the switch work.

Perhaps a better opening would have been a "what have you tried so far and why".

Then I could explain my approach and post my debug patch for you to comment on and explain why it doesn't work.

Then there's no description of why you think this might help, granted it is done in the bcmrobo.c code and I believe it is done in my debug patch but a lot more is done in it too so I need an explanation .

raven-au wrote:
meuleman wrote:
raven-au wrote:

The switch is still a problem, it simply doesn't work and nothing I do seems to change that.

Could you try below patch? It probably will make the switch work.

Perhaps a better opening would have been a "what have you tried so far and why".

Then I could explain my approach and post my debug patch for you to comment on and explain why it doesn't work.

Then there's no description of why you think this might help, granted it is done in the bcmrobo.c code and I believe it is done in my debug patch but a lot more is done in it too so I need an explanation .

Sorry for that. My platform for the moment is not an R8000, but a Broadcom internal development board which is somewhat similar to the R8000 when it comes to the HW. It has a 4709 with three 43602 devices and the switch is a 53011/rev5 (yes they do exist as well). While running the OpenWRT on that I was having problems with the switch (no communication). There was no Rx interrupts in the bgmac and tx packets were getting tx complete interrupts, but nothing was transmitted on the line. I also have a 4708 with 43602 and that board does work. As was already identified in this thread the main difference is in the version of the  switch inside the SOC.

So first I went looking for historical changes in the bcmrobo.c (I work at broadcom) which could explain this problem, but nothing got added in the code. Then I started looking at the code differences applying changes up till this change which made my switch work. Of course it may not work for the R8000 as this holds a different switch, but it might. Anyway it works for me and I thought lets share the patch so maybe we can go on to the next hurdle (wifi) of which I know a little bit more. If it doesn't work then I'll try to get my hands on a r8000 and see if I can get that to work.

meuleman wrote:
raven-au wrote:
meuleman wrote:

Could you try below patch? It probably will make the switch work.

Perhaps a better opening would have been a "what have you tried so far and why".

Then I could explain my approach and post my debug patch for you to comment on and explain why it doesn't work.

Then there's no description of why you think this might help, granted it is done in the bcmrobo.c code and I believe it is done in my debug patch but a lot more is done in it too so I need an explanation .

Sorry for that. My platform for the moment is not an R8000, but a Broadcom internal development board which is somewhat similar to the R8000 when it comes to the HW. It has a 4709 with three 43602 devices and the switch is a 53011/rev5 (yes they do exist as well). While running the OpenWRT on that I was having problems with the switch (no communication). There was no Rx interrupts in the bgmac and tx packets were getting tx complete interrupts, but nothing was transmitted on the line. I also have a 4708 with 43602 and that board does work. As was already identified in this thread the main difference is in the version of the  switch inside the SOC.

So first I went looking for historical changes in the bcmrobo.c (I work at broadcom) which could explain this problem, but nothing got added in the code. Then I started looking at the code differences applying changes up till this change which made my switch work. Of course it may not work for the R8000 as this holds a different switch, but it might. Anyway it works for me and I thought lets share the patch so maybe we can go on to the next hurdle (wifi) of which I know a little bit more. If it doesn't work then I'll try to get my hands on a r8000 and see if I can get that to work.

Thanks for taking the time to explain your experience, that's appreciated and helpful.

Your experience and approach is similar to my own although the changes I have come up with haven't resolved my problem.

The assumption is that the switch revision is the factor and I had previously assumed the CPU on a BCM53011 rev5 was also on port eight, as it is on the BCM53012 (R8000), but in hind sight and in light of your comment that seems incorrect.

Once the switch detection code is changed then there is logic that does what your patch does already in my debug patch.

But there's quite a bit more in my debug patch too.
Setting the mac address and changes to vlan configuration etc.

If you have the time and enough motivation review my debug patch and offer any comments you think relevant.

This is the debug patch:

b53-debug

From: Ian Kent <raven@themaw.net>


---
 ...gmac-set-mac-address-in-b53_platform_data.patch |   17 ++
 .../generic/files/drivers/net/phy/b53/b53_common.c |  141 +++++++++++++++++---
 .../generic/files/drivers/net/phy/b53/b53_regs.h   |    7 +
 .../files/include/linux/platform_data/b53.h        |    2
 4 files changed, 149 insertions(+), 18 deletions(-)
 create mode 100644 target/linux/bcm53xx/patches-3.18/920-bgmac-set-mac-address-in-b53_platform_data.patch

diff --git a/target/linux/bcm53xx/patches-3.18/920-bgmac-set-mac-address-in-b53_platform_data.patch b/target/linux/bcm53xx/patches-3.18/920-bgmac-set-mac-address-in-b53_platform_data.patch
new file mode 100644
index 0000000..9660921
--- /dev/null
+++ b/target/linux/bcm53xx/patches-3.18/920-bgmac-set-mac-address-in-b53_platform_data.patch
@@ -0,0 +1,17 @@
+bgmac: set mac address in b53_platform_data
+
+The R8000 needs the device mac address for switch setup.
+Pass it to the b53 driver in the b53_platform_data struct.
+
+Signed-off-by: Ian Kent <raven@themaw.net>
+--- a/drivers/net/ethernet/broadcom/bgmac.c
++++ b/drivers/net/ethernet/broadcom/bgmac.c
+@@ -1589,6 +1589,8 @@ static int bgmac_probe(struct bcma_devic
+           !bgmac_b53_pdata.regs) {
+               bgmac_b53_pdata.regs = ioremap_nocache(0x18007000, 0x1000);
+ 
++              memcpy(bgmac_b53_pdata.mac, mac, ETH_ALEN);
++
+               err = platform_device_register(&bgmac_b53_dev);
+               if (!err)
+                       bgmac->b53_device = &bgmac_b53_dev;
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
index 4597742..f3d57c8 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
@@ -415,8 +415,29 @@ static void b53_enable_mib(struct b53_device *dev)
        b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 }

+static void b53_set_arl_vlan_info(struct b53_device *dev, u8 *mac, int vid)
+{
+       u32 vport;
+       u8 val8;
+
+       b53_write8(dev, B53_ARLIO_PAGE, B53_VT_VID_INDEX, vid);
+
+       mac[6] = vid;
+       mac[7] = 0;
+       b53_write64(dev, B53_ARLIO_PAGE, B53_VT_ARL_E0, (u64) *mac);
+
+       vport = 0x18000 + dev->sw_dev.cpu_port;
+       b53_write32(dev, B53_ARLIO_PAGE, B53_VT_DAT_E0, vport);
+
+       val8 = 0x80;
+       b53_write8(dev, B53_ARLIO_PAGE, B53_VT_RW_CTRL, val8);
+
+       udelay(100);
+}
+
 static int b53_apply(struct b53_device *dev)
 {
+       u8 mac[8];
        int i;

        /* clear all vlan entries */
@@ -429,11 +450,21 @@ static int b53_apply(struct b53_device *dev)

        b53_enable_vlan(dev, dev->enable_vlan);

+       if (is5301x(dev) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
+               for (i = 5; i >= 0; i--)
+                       mac[5 - i] = dev->pdata.mac[i];
+               b53_write48(dev, B53_ARLIO_PAGE, B53_VT_MAC_INDEX, (u64) *mac);
+       }
+
        /* fill VLAN table */
        if (dev->enable_vlan) {
                for (i = 0; i < dev->sw_dev.vlans; i++) {
                        struct b53_vlan *vlan = &dev->vlans[i];

+                       if (is5301x(dev) &&
+                           dev->sw_dev.cpu_port == B53_CPU_PORT)
+                               b53_set_arl_vlan_info(dev, mac, i);
+
                        if (!vlan->members)
                                continue;

@@ -445,6 +476,10 @@ static int b53_apply(struct b53_device *dev)
                                    B53_VLAN_PORT_DEF_TAG(i),
                                    dev->ports[i].pvid);
        } else {
+               if (is5301x(dev) &&
+                   dev->sw_dev.cpu_port == B53_CPU_PORT)
+                       b53_set_arl_vlan_info(dev, mac, 1);
+
                b53_for_each_port(dev, i)
                        b53_write16(dev, B53_VLAN_PAGE,
                                    B53_VLAN_PORT_DEF_TAG(i), 1);
@@ -480,7 +515,7 @@ static void b53_switch_reset_gpio(struct b53_device *dev)

 static int b53_switch_reset(struct b53_device *dev)
 {
-       u8 mgmt;
+       u8 mgmt, rv;

        b53_switch_reset_gpio(dev);

@@ -534,26 +569,83 @@ static int b53_switch_reset(struct b53_device *dev)
                           mii_port_override | PORT_OVERRIDE_EN |
                           PORT_OVERRIDE_LINK);
        } else if (is5301x(dev)) {
-               /*
-                * CPU interface attached to port 8 requires specific handling.
-                * It uses different overriding register and extra ports 5 and 7
-                * need to be configured as well.
-                */
-               if (dev->sw_dev.cpu_port == 8) {
-                       u8 mii_port_override;
+               int i;

-                       b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
-                                 &mii_port_override);
-                       mii_port_override |= PORT_OVERRIDE_LINK |
-                                            PORT_OVERRIDE_RX_FLOW |
-                                            PORT_OVERRIDE_TX_FLOW |
-                                            PORT_OVERRIDE_SPEED_2000M |
-                                            PORT_OVERRIDE_EN;
-                       b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
-                                  mii_port_override);
+               /* No spanning tree for unmanaged mode */
+               rv = 0;
+               b53_for_each_port(dev, i)
+                       b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(i), rv);
+
+               if (dev->sw_dev.cpu_port == B53_CPU_PORT_25) {
+                       b53_read8(dev, B53_CTRL_PAGE,
+                                 B53_GMII_PORT_OVERRIDE_CTRL(B53_CPU_PORT_25),
+                                 &rv);
+                       rv |= PORT_OVERRIDE_LINK |
+                             PORT_OVERRIDE_RX_FLOW |
+                             PORT_OVERRIDE_TX_FLOW |
+                             PORT_OVERRIDE_SPEED_2000M |
+                             PORT_OVERRIDE_EN;
+                       b53_write8(dev, B53_CTRL_PAGE,
+                                  B53_GMII_PORT_OVERRIDE_CTRL(B53_CPU_PORT_25),
+                                  rv);
                } else {
-                       pr_warn("overriding CPU port other than 8 is not supported yet\n");
+                       /*
+                        * CPU interface attached to port 8 requires specific handling.
+                        * It uses different overriding register and extra ports 5 and 7
+                        * need to be configured as well.
+                        */
+                       b53_read8(dev, B53_CTRL_PAGE,
+                                 B53_PORT_OVERRIDE_CTRL, &rv);
+                       rv |= PORT_OVERRIDE_LINK |
+                             PORT_OVERRIDE_RX_FLOW |
+                             PORT_OVERRIDE_TX_FLOW |
+                             PORT_OVERRIDE_SPEED_2000M |
+                             PORT_OVERRIDE_EN;
+                       b53_write8(dev, B53_CTRL_PAGE,
+                                  B53_PORT_OVERRIDE_CTRL, rv);
+
+                       b53_read8(dev, B53_CTRL_PAGE,
+                                 B53_PORT_CTRL(B53_CPU_PORT), &rv);
+                       rv |= PORT_CTRL_RX_UCST_EN |
+                             PORT_CTRL_RX_MCST_EN |
+                             PORT_CTRL_RX_BCST_EN;
+                       b53_write8(dev, B53_CTRL_PAGE,
+                                  B53_PORT_CTRL(B53_CPU_PORT), rv);
+
+                       b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &rv);
+                       rv |= GC_FRM_MGMT_PORT_MII;
+                       b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, rv);
+
+                       b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &rv);
+                       rv |= VC5_RX_BYPASS_CRC;
+                       b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, rv);
+
+                       /* Set managed mode */
+                       b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &rv);
+                       rv |= SM_SW_FWD_MODE;
+                       b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, rv);
+
+                       /* Enable ports 5 and 7 for SMP dual core GMAC 3 */
+                       b53_read8(dev, B53_CTRL_PAGE,
+                                 B53_GMII_PORT_OVERRIDE_CTRL(5), &rv);
+                       rv &= ~(GMII_PORT_OVERRIDE_LINK);
+                       b53_write8(dev, B53_CTRL_PAGE,
+                                  B53_GMII_PORT_OVERRIDE_CTRL(5), rv);
+
+                       b53_read8(dev, B53_CTRL_PAGE,
+                                 B53_GMII_PORT_OVERRIDE_CTRL(7), &rv);
+                       rv &= ~(GMII_PORT_OVERRIDE_LINK);
+                       b53_write8(dev, B53_CTRL_PAGE,
+                                  B53_GMII_PORT_OVERRIDE_CTRL(7), rv);
                }
+
+               rv = 0;
+
+               /* Disable BRCM HDR */
+               b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, rv);
+
+               /* Disable CFP */
+               b53_write8(dev, B53_CFP_PAGE, B53_CFP_CTRL, rv);
        }

        b53_enable_mib(dev);
@@ -1304,6 +1396,19 @@ static int b53_switch_init(struct b53_device *dev)
                /* use second IMP port if GMII is enabled */
                if (strap_value & SV_GMII_CTRL_115)
                        sw_dev->cpu_port = 5;
+       } else if (dev->chip_id == BCM53012_DEVICE_ID && dev->core_rev > 3) {
+               /* Later revisions of these devices use a different
+                * cpu port and have additional setup needs. Ports 5
+                * and 7 are related to the dual core cpu and need to
+                * be included, port 8 is the cpu port.  Port 6 is not
+                * usable.
+                *
+                * NOTE: this only checks if BCM53012 devices have a
+                * revision > 3 but other devices in the BCM5301x
+                * family might need additional handling.
+                */
+               dev->enabled_ports = 0xbf;
+               sw_dev->cpu_port = B53_CPU_PORT;
        }

        /* cpu port is always last */
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index 8a6e242..4888bba 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -192,6 +192,12 @@
  * ARL Access Page Registers
  *************************************************************************/

+#define B53_VT_RW_CTRL                 0x00 /* ARL R/W control */
+#define B53_VT_MAC_INDEX               0x02 /* MAC address index */
+#define B53_VT_VID_INDEX               0x08 /* VID table index */
+#define B53_VT_ARL_E0                  0x10 /* */
+#define B53_VT_DAT_E0                  0x18 /* */
+
 /* VLAN Table Access Register (8 bit) */
 #define B53_VT_ACCESS                  0x80
 #define B53_VT_ACCESS_9798             0x60 /* for BCM5397/BCM5398 */
@@ -282,6 +288,7 @@
 #define B53_VLAN_CTRL5                 0x06
 #define B53_VLAN_CTRL5_25              0x05
 #define B53_VLAN_CTRL5_63XX            0x07
+#define   VC5_RX_BYPASS_CRC            BIT(0)
 #define   VC5_VID_FFF_EN               BIT(2)
 #define   VC5_DROP_VTABLE_MISS         BIT(3)

diff --git a/target/linux/generic/files/include/linux/platform_data/b53.h b/target/linux/generic/files/include/linux/platform_data/b53.h
index 7842741..b1af3c4 100644
--- a/target/linux/generic/files/include/linux/platform_data/b53.h
+++ b/target/linux/generic/files/include/linux/platform_data/b53.h
@@ -28,6 +28,8 @@ struct b53_platform_data {
        /* allow to specify an ethX alias */
        const char *alias;

+       u8 mac[6];
+
        /* only used by MMAP'd driver */
        unsigned big_endian:1;
        void __iomem *regs;

The other two patches applied here from @zajec (that you would need for comparison if you did so) are:

b53: define registers available and needed on BCM5301X

From: Rafal Milecki <zajec5@gmail.com>

They are also present on some BCM63xx switches.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 .../generic/files/drivers/net/phy/b53/b53_regs.h   |   32 ++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index 4899cc4..cd1ea6d 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -50,6 +50,9 @@
 /* Jumbo Frame Registers */
 #define B53_JUMBO_PAGE                 0x40

+/* CFP Configuration Registers Page */
+#define B53_CFP_PAGE                   0xa1
+
 /*************************************************************************
  * Control Page registers
  *************************************************************************/
+/*
+ * Overriding ports 0-7 on devices with xMII interfaces (8 bit)
+ * For port 8 still use B53_PORT_OVERRIDE_CTRL
+ * Please note that not all ports are available on every hardware, e.g. BCM5301X
+ * don't include overriding port 6, BCM63xx also have some limitations.
+ */
+#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + i)
+#define   GMII_PORT_OVERRIDE_LINK              BIT(0)
+#define   GMII_PORT_OVERRIDE_FULL_DUPLEX       BIT(1) /* 0 = Half Duplex */
+#define   GMII_PORT_OVERRIDE_SPEED_S           2
+#define   GMII_PORT_OVERRIDE_SPEED_10M         (0 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_SPEED_100M                (1 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_SPEED_1000M       (2 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_RX_FLOW           BIT(4)
+#define   GMII_PORT_OVERRIDE_TX_FLOW           BIT(5)
+#define   GMII_PORT_OVERRIDE_EN                        BIT(6) /* Use the register contents */
+#define   GMII_PORT_OVERRIDE_SPEED_2000M       BIT(7) /* BCM5301X only, requires setting 1000M */
+
 /* Software reset register (8 bit) */
 #define B53_SOFTRESET                  0x79

@@ -156,6 +177,10 @@
 #define   GC_FRM_MGMT_PORT_04          0x00
 #define   GC_FRM_MGMT_PORT_MII         0x80

+/* Enable BCM_HDR Tag on IMP port (8 bit) */
+#define B53_BRCM_HDR                   0x03
+#define   BRCM_HDR_EN                  BIT(0)
+
 /* Device ID register (8 or 32 bit) */
 #define B53_DEVICE_ID                  0x30

@@ -310,4 +335,11 @@
 #define   JMS_MIN_SIZE                 1518
 #define   JMS_MAX_SIZE                 9724

+/*************************************************************************
+ * CFP Configuration Page Registers
+ *************************************************************************/
+
+/* CFP Control Register with ports map (8 bit) */
+#define B53_CFP_CTRL                   0x00
+
 #endif /* !__B53_REGS_H */
b53: fix overriding port 8 state (if it is connected to CPU)

From: Rafał Miłecki <zajec5@gmail.com>

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 .../generic/files/drivers/net/phy/b53/b53_common.c |   23 +++++++++++++++++++-
 .../generic/files/drivers/net/phy/b53/b53_regs.h   |    1 +
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
index e44d194..4597742 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
@@ -525,7 +525,7 @@ static int b53_switch_reset(struct b53_device *dev)
                                return -EINVAL;
                        }
                }
-       } else if ((is531x5(dev) || is5301x(dev)) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
+       } else if (is531x5(dev) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
                u8 mii_port_override;

                b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
@@ -533,6 +533,27 @@ static int b53_switch_reset(struct b53_device *dev)
                b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
                           mii_port_override | PORT_OVERRIDE_EN |
                           PORT_OVERRIDE_LINK);
+       } else if (is5301x(dev)) {
+               /*
+                * CPU interface attached to port 8 requires specific handling.
+                * It uses different overriding register and extra ports 5 and 7
+                * need to be configured as well.
+                */
+               if (dev->sw_dev.cpu_port == 8) {
+                       u8 mii_port_override;
+
+                       b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
+                                 &mii_port_override);
+                       mii_port_override |= PORT_OVERRIDE_LINK |
+                                            PORT_OVERRIDE_RX_FLOW |
+                                            PORT_OVERRIDE_TX_FLOW |
+                                            PORT_OVERRIDE_SPEED_2000M |
+                                            PORT_OVERRIDE_EN;
+                       b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
+                                  mii_port_override);
+               } else {
+                       pr_warn("overriding CPU port other than 8 is not supported yet\n");
+               }
        }

        b53_enable_mib(dev);
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index cd1ea6d..8a6e242 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -86,6 +86,7 @@
 #define   PORT_OVERRIDE_RV_MII_25      BIT(4) /* BCM5325 only */
 #define   PORT_OVERRIDE_RX_FLOW                BIT(4)
 #define   PORT_OVERRIDE_TX_FLOW                BIT(5)
+#define   PORT_OVERRIDE_SPEED_2000M    BIT(6) /* BCM5301X only, requires setting 1000M */
 #define   PORT_OVERRIDE_EN             BIT(7) /* Use the register contents */

 /* Power-down mode control */
meuleman wrote:

So first I went looking for historical changes in the bcmrobo.c (I work at broadcom) which could explain this problem, but nothing got added in the code. Then I started looking at the code differences applying changes up till this change which made my switch work. Of course it may not work for the R8000 as this holds a different switch, but it might. Anyway it works for me and I thought lets share the patch so maybe we can go on to the next hurdle (wifi) of which I know a little bit more. If it doesn't work then I'll try to get my hands on a r8000 and see if I can get that to work.

The wifi, yes, that's the next problem.
Interestingly my motivation for starting to work with OpenWrt was to start to develop an understanding of wifi and wifi drivers, which I really haven't got to yet.

You mentioned your board has three 43602 devices, are two of them connected via a PEX8603 as they are on the R8000?
The PEX8603 caused all sorts of problems, lots of invalid and non-existent devices got created in the pci device tree.
You've probably seen my patch for that but I can forward it if you need it, of course it may not be quite right either.

For my part I see the brcmfmac driver populates sysfs and wifi detect runs through to completion.
However, the driver insists the chips are 2.4 GHz only and objects to 5Ghz wifi changes for the device.

A while back you'll see a post of my wireless configuration that clearly has wrong channel numbers, believe me, that's not the cause of the problem.

Other than that I believe the switch not working limits what can be tested with the wifi devices anyway, although you do have a working switch so maybe we can make some progress with the wifi.

(Last edited by raven-au on 11 Apr 2015, 05:32)

raven-au wrote:

The wifi, yes, that's the next problem.
Interestingly my motivation for starting to work with OpenWrt was to start to develop an understanding of wifi and wifi drivers, which I really haven't got to yet.

You mentioned your board has three 43602 devices, are two of them connected via a PEX8603 as they are on the R8000?
The PEX8603 caused all sorts of problems, lots of invalid and non-existent devices got created in the pci device tree.
You've probably seen my patch for that but I can forward it if you need it, of course it may not be quite right either.

For my part I see the brcmfmac driver populates sysfs and wifi detect runs through to completion.
However, the driver insists the chips are 2.4 GHz only and objects to 5Ghz wifi changes for the device.

A while back you'll see a post of my wireless configuration that clearly has wrong channel numbers, believe me, that's not the cause of the problem.

Other than that I believe the switch not working limits what can be tested with the wifi devices anyway, although you do have a working switch so maybe we can make some progress with the wifi.

Tried the image on an r8000 last friday and the switch is working. Since I have some more changes made I will do a clean checkout on Monday and only apply the b53 patch to see if that makes the switch working.

The dev board I'm using is slightly diferent from the R8000, also the devices (43602) are connected differently I think (at least they show up with different domain/bus nrs on the pci). I'm quite unfamiliar with the 4709 and its PCIE bus so I hope there are no big issues to overcome, but sofar the openwrt drivers appear to be working fine for me.

When booting the r8000 and internal dev board I get the same result, only one wifi module really works, but they are all there. The reason for that is the missing nvram information. The problem with that is that the brcmfmac can not parse the nvram data from APs. As a matter of fact, the current version of brcmfmac can not even deal with multiple devices of the same type, well it can, but no seperate nvram data can be loaded per device. Last friday I made a patch which can deal with more complex nvram files and handle the compressed and non-compressed multi pcie nvram files. I've tested it with the nvram file of an r8000 (and parsing went fine) and tested it live on our dev board and now all wifi devices got deteced properly. I could configure them via luci and did an iperf test (via the switch) and had over 300Mbit TCP. This is not spectacular but it is working and since the 4709 is only a 1G dual core speeds wont get much higher (due to bridging etc.), it is cpu bound.

I've had no time yet to test this on the r8000 but intend to do this coming week. There is one more kernel patche required (configuring the L2 cache ctrl register properly) and I will also sent that out as soon as I've done the verification. I'm pretty sure we should be able to get the r8000 fully functional up and running in the coming weeks, but there are issues which need fixing.

So to come back to your question about the detection of the devices. I'm pretty sure that once the correct nvram data is pushed in the device by brcmfmac then the devices will be detected correctly and operate properly. The patch is submitted for review (internally in BRCM) and will then go out to the wireless tree. From there it will at some point make it into compat wireless but that will take some while. So I will create a zip of the brcmfmac with the patches as I use it on the dev board and r8000 so it can be tested till compat-wrireless has been updated. The only requirement will be that an nvram file will be created from nvram datastore which gets put in the file /lib/firmware/brcm/brcmfmac43602-pcie.txt. No filter is required on the contents. So the complete nvram can be put in there and the fmac will do the parsing.

raven-au wrote:

The other two patches applied here from @zajec (that you would need for comparison if you did so) are:

b53: define registers available and needed on BCM5301X

From: Rafal Milecki <zajec5@gmail.com>

They are also present on some BCM63xx switches.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 .../generic/files/drivers/net/phy/b53/b53_regs.h   |   32 ++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index 4899cc4..cd1ea6d 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -50,6 +50,9 @@
 /* Jumbo Frame Registers */
 #define B53_JUMBO_PAGE                 0x40

+/* CFP Configuration Registers Page */
+#define B53_CFP_PAGE                   0xa1
+
 /*************************************************************************
  * Control Page registers
  *************************************************************************/
+/*
+ * Overriding ports 0-7 on devices with xMII interfaces (8 bit)
+ * For port 8 still use B53_PORT_OVERRIDE_CTRL
+ * Please note that not all ports are available on every hardware, e.g. BCM5301X
+ * don't include overriding port 6, BCM63xx also have some limitations.
+ */
+#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + i)
+#define   GMII_PORT_OVERRIDE_LINK              BIT(0)
+#define   GMII_PORT_OVERRIDE_FULL_DUPLEX       BIT(1) /* 0 = Half Duplex */
+#define   GMII_PORT_OVERRIDE_SPEED_S           2
+#define   GMII_PORT_OVERRIDE_SPEED_10M         (0 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_SPEED_100M                (1 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_SPEED_1000M       (2 << PORT_OVERRIDE_SPEED_S)
+#define   GMII_PORT_OVERRIDE_RX_FLOW           BIT(4)
+#define   GMII_PORT_OVERRIDE_TX_FLOW           BIT(5)
+#define   GMII_PORT_OVERRIDE_EN                        BIT(6) /* Use the register contents */
+#define   GMII_PORT_OVERRIDE_SPEED_2000M       BIT(7) /* BCM5301X only, requires setting 1000M */
+
 /* Software reset register (8 bit) */
 #define B53_SOFTRESET                  0x79

@@ -156,6 +177,10 @@
 #define   GC_FRM_MGMT_PORT_04          0x00
 #define   GC_FRM_MGMT_PORT_MII         0x80

+/* Enable BCM_HDR Tag on IMP port (8 bit) */
+#define B53_BRCM_HDR                   0x03
+#define   BRCM_HDR_EN                  BIT(0)
+
 /* Device ID register (8 or 32 bit) */
 #define B53_DEVICE_ID                  0x30

@@ -310,4 +335,11 @@
 #define   JMS_MIN_SIZE                 1518
 #define   JMS_MAX_SIZE                 9724

+/*************************************************************************
+ * CFP Configuration Page Registers
+ *************************************************************************/
+
+/* CFP Control Register with ports map (8 bit) */
+#define B53_CFP_CTRL                   0x00
+
 #endif /* !__B53_REGS_H */
b53: fix overriding port 8 state (if it is connected to CPU)

From: Rafał Miłecki <zajec5@gmail.com>

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 .../generic/files/drivers/net/phy/b53/b53_common.c |   23 +++++++++++++++++++-
 .../generic/files/drivers/net/phy/b53/b53_regs.h   |    1 +
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
index e44d194..4597742 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_common.c
@@ -525,7 +525,7 @@ static int b53_switch_reset(struct b53_device *dev)
                                return -EINVAL;
                        }
                }
-       } else if ((is531x5(dev) || is5301x(dev)) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
+       } else if (is531x5(dev) && dev->sw_dev.cpu_port == B53_CPU_PORT) {
                u8 mii_port_override;

                b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
@@ -533,6 +533,27 @@ static int b53_switch_reset(struct b53_device *dev)
                b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
                           mii_port_override | PORT_OVERRIDE_EN |
                           PORT_OVERRIDE_LINK);
+       } else if (is5301x(dev)) {
+               /*
+                * CPU interface attached to port 8 requires specific handling.
+                * It uses different overriding register and extra ports 5 and 7
+                * need to be configured as well.
+                */
+               if (dev->sw_dev.cpu_port == 8) {
+                       u8 mii_port_override;
+
+                       b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
+                                 &mii_port_override);
+                       mii_port_override |= PORT_OVERRIDE_LINK |
+                                            PORT_OVERRIDE_RX_FLOW |
+                                            PORT_OVERRIDE_TX_FLOW |
+                                            PORT_OVERRIDE_SPEED_2000M |
+                                            PORT_OVERRIDE_EN;
+                       b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
+                                  mii_port_override);
+               } else {
+                       pr_warn("overriding CPU port other than 8 is not supported yet\n");
+               }
        }

        b53_enable_mib(dev);
diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
index cd1ea6d..8a6e242 100644
--- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
+++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
@@ -86,6 +86,7 @@
 #define   PORT_OVERRIDE_RV_MII_25      BIT(4) /* BCM5325 only */
 #define   PORT_OVERRIDE_RX_FLOW                BIT(4)
 #define   PORT_OVERRIDE_TX_FLOW                BIT(5)
+#define   PORT_OVERRIDE_SPEED_2000M    BIT(6) /* BCM5301X only, requires setting 1000M */
 #define   PORT_OVERRIDE_EN             BIT(7) /* Use the register contents */

 /* Power-down mode control */

I reviewed these patches and they are the same except for one thing: the CPU port will not be 8 but it will be B53_CPU_PORT_25, see the b53_switch_chips array. This define is 5 (see b53_priv.h). Also it should not have accessed the register B53_PORT_OVERRIDE_CTRL, but used the new define B53_GMII_PORT_OVERRIDE_CTRL(i) where i would have been dev->sw_dev.cpu_port. Of course that would be for the read and the write. So this line:

+                       b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
+                                 &mii_port_override);

should be change into:

+                       b53_read8(dev, B53_CTRL_PAGE, B53_GMII_PORT_OVERRIDE_CTRL(dev->sw_dev.cpu_port),
+                                 &mii_port_override);

And the same goes for b53_write. So my patch is different in that it does not check for CPU id, but just uses it, and addresses a different register based upon cpu id. This was obviously also the intention with the patch from zajec as the macro B53_GMII_PORT_OVERRIDE_CTRL(i) is there, but it just isnt used (copy/paste bug would be my guess).

@meuleman: can you provide output of "nvram show | grep ports=" from your devices? Internal board and your R8000?

(Last edited by Zajec on 12 Apr 2015, 23:14)

Zajec wrote:

@meuleman: can you provide output of "nvram show | grep ports=" from your devices? Internal board and your R8000?

R8000:

vlan2ports=4 8u
vlan1ports=3 2 1 0 5 7 8*

Dev board:

vlan2ports=0 8u
vlan1ports=1 2 3 4 5 7 8*

Did a clean checkout this morning and saw that b53 code got updated. Did a build (only changing chk type image to trx) and than ran that on r8000, and switch is working now, thank you @Zajec.

Now for the wifi.

Got the WiFi up and running, but a couple of patches are needed.

1) The kernel needs a patch for a l2 cache setup bug. The CFE is supposed to set a bit (22) in the l2 aux ctrl register. This is not done by all CFEs and as a result there can be issues with reading data which gets DMA'ed by the 43602 to the host. I've updated the file cache-l2x0.c in the kernel but dont know how to create a patch from that. See this link for info:
https://groups.google.com/forum/#!topic … jfn8Kb7dvY
2) There are a couple of issues with brcmfmac:
  a) The r8000 I'm having is using pcie device id 0xAA52, so we have to add that to the list of supported devices. A patch will be created for that and put under review.
  b) multiple nvram device entry support is needed. A patch was created for that and still under review, but almost accepted. There is a requirement though for this to work: the nvram contents should be copied into the file /lib/firmware/brcm/brcmfmac43602-pcie.txt. The contents holds device specific information (like MAC adddress) and needs to be created on the device. For my testing I did create it from the CFE and manually put it on the device after the first boot.
c) A critical patch was not yet in the version of backports (compat wireless) which got synced.

What would be the way to go forward? I can share my version of cache-l2x0.c? The fmac patches will eventually end up in backports but it will take some time. I can share my version.

Hereby a patch which will fix the l2 cache problem. This patch updates an existing patch which already did an override on the l2 aux ctrl. With this patch bit 22 gets set correctly and all l2 cache problems should be fixed. The updates on the patch were handmade but verified to be working. So the patch applies and when the debug output on the console indicates that bit 22 gets set.

An internal patch for the 0xaa52 (43602) pcie device id was created and is under review. All necessary patches for brcmfmac will hopefully be published before end of this week.


diff --git a/target/linux/bcm53xx/patches-3.18/305-ARM-BCM53XX-set-customized-AUXCTL.patch b/target/linux/bcm53xx/patches-3.18/305-ARM-BCM53XX-set-customized-AUXCTL.patch
index ab35ca6..50be30b 100644
--- a/target/linux/bcm53xx/patches-3.18/305-ARM-BCM53XX-set-customized-AUXCTL.patch
+++ b/target/linux/bcm53xx/patches-3.18/305-ARM-BCM53XX-set-customized-AUXCTL.patch
@@ -10,16 +10,17 @@ This is based on some vendor code
 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
 ---
  arch/arm/mach-bcm/bcm_5301x.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
+ 1 file changed, 6 insertions(+), 1 deletion(-)
 
 --- a/arch/arm/mach-bcm/bcm_5301x.c
 +++ b/arch/arm/mach-bcm/bcm_5301x.c
-@@ -50,7 +50,11 @@ static const char __initconst *bcm5301x_
+@@ -50,7 +50,12 @@ static const char __initconst *bcm5301x_
  };
  
  DT_MACHINE_START(BCM5301X, "BCM5301X")
 -      .l2c_aux_val    = 0,
-+      .l2c_aux_val    = L310_AUX_CTRL_CACHE_REPLACE_RR |
++      .l2c_aux_val    = L310_AUX_CTRL_SH_ATTR_OVERRIDE_ENABLE |
++                        L310_AUX_CTRL_CACHE_REPLACE_RR |
 +                        L310_AUX_CTRL_DATA_PREFETCH |
 +                        L310_AUX_CTRL_INSTR_PREFETCH |
 +                        L310_AUX_CTRL_EARLY_BRESP |
@@ -27,3 +28,14 @@ Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
        .l2c_aux_mask   = ~0,
        .init_early     = bcm5301x_init_early,
        .dt_compat      = bcm5301x_dt_compat,
+--- a/arch/arm/include/asm/hardware/cache-l2x0.h
++++ b/arch/arm/include/asm/hardware/cache-l2x0.h
+@@ -121,6 +121,7 @@
+ #define L310_AUX_CTRL_STORE_LIMITATION                BIT(11) /* R2P0+ */
+ #define L310_AUX_CTRL_EXCLUSIVE_CACHE         BIT(12)
+ #define L310_AUX_CTRL_ASSOCIATIVITY_16                BIT(16)
++#define L310_AUX_CTRL_SH_ATTR_OVERRIDE_ENABLE BIT(22)
+ #define L310_AUX_CTRL_CACHE_REPLACE_RR                BIT(25) /* R2P0+ */
+ #define L310_AUX_CTRL_NS_LOCKDOWN             BIT(26)
+ #define L310_AUX_CTRL_NS_INT_CTRL             BIT(27)
+
meuleman wrote:

c) A critical patch was not yet in the version of backports (compat wireless) which got synced.

Point it...

Zajec wrote:
meuleman wrote:

c) A critical patch was not yet in the version of backports (compat wireless) which got synced.

Point it...

https://git.kernel.org/cgit/linux/kerne … afb34d5d44

Without that patch a timeout on ioctl can occur.

The other two brcmfmac patches have been reviewed internally but not posted yet.

Added in r45432

Totally forgot about the bgmac bug. There is locking mechanism missing for the queue stopping/waking. When doing iperf (> 400Mbit) TCP from ethernet to wifi client then you'll end up in stopped situation. This is due to fact that while code has decided to stop the queue, but before actually doing so, all tx completes have been handled (by other CPU/thread). In this situation the queue gets stopped, but never woken, therefor the check with the actual stop has to be protected by a lock and at the same time the wake has to be protected with the same lock.

This is the diff/patch which needs to be applied on bgmac.c:

--- ./build_dir/target-arm_cortex-a9_uClibc-0.9.33.2_eabi/linux-bcm53xx/linux-3.18.11/drivers/net/ethernet/broadcom/bgmac.c    2015-04-14 16:37:32.880287147 +0200
+++ ../openwrt/build_dir/target-arm_cortex-a9_uClibc-0.9.33.2_eabi/linux-bcm53xx/linux-3.18.11/drivers/net/ethernet/broadcom/bgmac.c    2015-04-13 11:54:44.079146686 +0200
@@ -27,8 +27,6 @@
 };
 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
 
+static DEFINE_SPINLOCK(queue_lock);
+
 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
                  u32 value, int timeout)
 {
@@ -209,10 +207,8 @@
             (ring->end % BGMAC_TX_RING_SLOTS) *
             sizeof(struct bgmac_dma_desc));
 
+    spin_lock(&queue_lock);
     if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
         netif_stop_queue(net_dev);
+    spin_unlock(&queue_lock);
 
     return NETDEV_TX_OK;
 
@@ -291,10 +287,8 @@
 
     netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
 
+    spin_lock(&queue_lock);
     if (netif_queue_stopped(bgmac->net_dev))
         netif_wake_queue(bgmac->net_dev);
+    spin_unlock(&queue_lock);
 }

(Last edited by meuleman on 14 Apr 2015, 18:12)

Sorry, posts 101 to 100 are missing from our archive.